Re: [vhdl-200x] Interfaces with normal, conjugated and monitor flavours

On 05/03/15 21:14, Ernst Christen wrote:
> Brent, Andy, Tristan,

[...]

Focusing on the pure AMS part:

> I am advocating that an interface be more flexible than this, that it should be extensible to allow the inclusion of terminals and quantities. This precludes a type as a starting point, and it makes the interface concept a new construct that bundles object declarations, something like
>
>     interface r_cpu_bus is
>         adr:  std_logic_vector(15 downto 0);  -- Address
>         dat:  std_logic_vector(15 downto 0);  -- Data between master and slave
>         cs:   std_logic_vector(7 downto 0);   -- ChipSelect-bus from master
>         we:   std_logic;                      -- Write enable from master
>         en:   std_logic;                      -- Enable from master
>         ack:  std_logic;                      -- Acknowledge from slave
>         err:  std_logic;                      -- Error from slave
>         terminal t1: electrical_vector(7 downto 0);  -- Added to demonstrate VHDL-AMS
> 	   quantity q: real                    -- Added to demonstrate VHDL-AMS
>     end interface r_cpu_bus;

To my understanding, there is an issue with 'quantity': a 
interface_quantity_declaration is very different from a 
quantity_declaration, so you cannot create objects using an interface:

interface xxx : r_cpu_bus;

This works with signals and terminals but not with a quantity.
I might be wrong, but to my understanding this is a serious issue when
considering AMS.  (And unfortunately, I have no ideas to solve that
except big hammer rule as explained below but I am not an AMS expert).

According to your syntax, we could add object class like constant (?), 
variable or signal (the latter being the default).  That would be nice,
but don't forget that variable and signal are almost always
incompatible.  One possible solution is to not allow object declaration
from an interface where not possible (this would include quantity).

Tristan.


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