RE: EXTERNAL: RE: [vhdl-200x] Interfaces with normal, conjugated and monitor flavours

The SystemVerilog interface design started from a different place.  There was no way of bundling signals in Verilog, whereas VHDL has record signals.  The problem being addressed is applying different modes to the components of the record, like the modport construct in SV.  It turns out that defining the modport construct within the interface is sometimes inconvenient, and it might have been better to define it separately, because changing the interface affects the modport.  In VHDL we need to consider how changing the record type of the signal will affect the port map.

 

Peter Flake

 

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Ben Cohen
Sent: 05 March 2015 09:28
To: vhdl-200x@eda.org
Subject: Re: EXTERNAL: RE: [vhdl-200x] Interfaces with normal, conjugated and monitor flavours

 

My apologies for not following all of this thread; However, I fail to understand why you don't use the SV interface model.  In SV, an interface is an object, just like a port. This it is a type.  It works pretty much like a module in that you can have assertions, functions, assigns, and always blocks. It also has mod ports to support the usage of the interface.

I am sure that missed something, but a lot of thought went into the SV interface. 

 

Ben Cohen 


On Thursday, March 5, 2015, <John.Aasen@kongsberg.com> wrote:

I would want to use interfaces for the transaction side of a bus functional model in my testbenches. To complete a transaction interface I use procedures. It would strongly reduce the usefulness of interfaces if I cannot use the interface in a procedure.

So I think interfaces needs to be a type and must be allowed to be used everywhere a type is used.

John

> -----Original Message-----
> From: owner-vhdl-200x@eda.org <javascript:;>  [mailto:owner-vhdl-200x@eda.org <javascript:;> ] On
> Behalf Of tgingold@free.fr <javascript:;> 
> Sent: 5. mars 2015 09:29
> To: vhdl-200x@eda.org <javascript:;> 
> Subject: Re: EXTERNAL: RE: [vhdl-200x] Interfaces with normal, conjugated
> and monitor flavours
>
> > I don’t see how we can avoid a means of associating a type with one or
> > more interfaces. Interfaces don’t get associated to just other
> > interfaces, they get associated with signal, constant and variable
> > (for subprograms) objects. And those objects have types.
>
> I strongly agree with this requirement.  The 'interface' could also be used to
> declare objects (but as I said this has important consequences).
>
> > Compatibility with subprograms (sequentially or concurrently called)
> > is also desirable.
>
> 'Desirable' is the right word IMHO; this is not a requirement.
>
> Tristan.
>
> --
> This message has been scanned for viruses and dangerous content by
> MailScanner, and is believed to be clean.
>
>


________________________________

CONFIDENTIALITY
This e-mail and any attachment contain KONGSBERG information which may be proprietary, confidential or subject to export regulations, and is only meant for the intended recipient(s). Any disclosure, copying, distribution or use is prohibited, if not otherwise explicitly agreed with KONGSBERG. If received in error, please delete it immediately from your system and notify the sender properly.

--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.





-- 
This message has been scanned for viruses and 
dangerous content by  <http://www.mailscanner.info/> MailScanner, and is 
believed to be clean. 


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.