Hi, A question came up in DASC, 1076's sponsoring committee, as to whether to withdraw 1076.4 (and 1076.6 although it is already withdrawn). 1076.4 is essential for FPGA gate level simulations. Rather than that, I am hoping that someone is interested in chairing these activities? Anyone interested in chairing one of these? If it were me, which it cannot be as I already have too much on my plate, my strategy would be to simply ballot the standard as it is in an attempt to simply re-affirm it. If someone ballots negative requesting a change, then simply invite them to be part of the committee for either that revision or the next. This would be a great way to learn the IEEE process. Best Regards, Jim On 1/26/2015 8:59 AM, Jim Lewis wrote: > Hi Stan, > At least for 1076.4 and likely 1076.6, we need to recruit someone from the FPGA vendor and/or user community to take responsibility for it. Are you able to reach out to the FPGA vendors? > > If a standard is balloted with the intention of "re-affirming". I suppose the ballot could fail because someone wants a revision to the standard. However, then at least you have surfaced a chair, > because if they were not willing to do the work, then their request has no relevance. > > Jim > >> Jim, >> >> As I indicated in my initial email, there is no possibility of simple “reaffirmation” in which an older standard basically is given an up-down vote. That reaffirmation path was ended several >> years ago. >> >> If 1076.4 and 1076.6 are not to be withdrawn, then a PAR must be written (and submitted to NesCom), a WG formed and a new (possibly unmodified) LRM must be put to a ballot and sent to RevCom. >> >> I was not part of the discussion behind the ending of the “reaffirmation” path, but I think the motivation was the same as the requirement to do a re-standardization process at least every 10 >> years. If there is no group of people that care enough about a standard to go through the WG process etc., how much of a living standard is it? >> >> That said, we can debate this all we want, but we are not going to change the process. If people want 1076.4 and 1076.6 to continue as current standards, action must be taken. >> >> Stan >> >> *From:*Jim Lewis [mailto:jim@synthworks.com] >> *Sent:* Monday, January 26, 2015 8:00 AM >> *To:* Stan Krolikoski; 'stds-dasc@eda.org' >> *Cc:* vhdl-200x@eda.org >> *Subject:* Re: FW: IEEE-CS-stabilized or withdrawn older DA standards? >> >> Hi Stan, >> 1076.4 Vital is a standard that is still actively used in the FPGA world. So it would be a bad thing to withdraw it. Key parties that benefit from its existence are FPGA and EDA vendors. >> Minimally it needs to be re-affirmed as is. >> >> I thought 1076.6 and 1364.1 were previously withdrawn. Anything we can do at this point to re-affirm 1076.6? It is difficult to claim submit bug reports against a vendors implementation against a >> withdrawn standard. >> >> Best Regards, >> Jim >> >> >> All, >> >> I received the email below from the IEEE CS, As you can see, there are four standards still listed as being sponsored by the DASC: >> >> 1076.4 VITAL >> >> 1076.6: VHDL RTL Synthesis subset >> >> 1364.1: Verilog RTL Synthesis subset >> >> 1603: ALF >> >> I propose to “take all of these off the books”, and have them all withdrawn. However, I would like to see if any DASC members object. If so, then we should discuss this via email and (if >> necessary) at our next meeting in February. On the other hand, if no one objects, I’ll work to have them withdrawn. >> >> BTW, if anyone is interested in reviving any of these, please note that a new WG will have to be formed, and the resulting LRM will have to go through a formal ballot procedure. The older >> process of ‘reaffirmation” of a standard no longer exists. >> >> Stan >> >> *From:* Annette Reilly [mailto:annetterieee@gmail.com] >> *Sent:* Saturday, January 24, 2015 11:22 AM >> *To:* Stan Krolikoski >> *Cc:* Don Wright >> *Subject:* IEEE-CS-stabilized or withdrawn older DA standards? >> >> Stan, >> >> I researching standards status for the IEEE-CS SAB meeting next week, I noticed that the DA sponsor has several standards that are coming up on 10 years and one more than 10 years old, which >> are jointly produced or adoptions of IEC standards. However, the IEC standards have since been withdrawn. This leaves IEEE with standards that should either be withdrawn or revised (IEEE-SA no >> longer allows “stabilized” standards). >> >> Could you let me know what the DASC is planning for these withdrawn IEC standards? >> >> 61691-5 (2004) IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages - Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification >> >> 62050 >> >> >> >> 2005 >> >> >> >> C/DA >> >> >> >> IEC 62050 Ed. 1 (IEEE Std 1076.6(TM)-2004): IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis >> >> 62142 >> >> >> >> 2005 >> >> >> >> C/DA >> >> >> >> IEC 62142 Ed. 1 (IEEE Std 1364.1(TM)-2002): Standard for Verilog(R) Register Transfer Level Synthesis >> >> 62265 >> >> >> >> 2005 >> >> >> >> C/DA >> >> >> >> IEC 62265 Ed. 1 (IEEE Std 1603(TM)-2003): Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks >> >> Thanks, >> >> Annette Reilly >> >> IEEE-CS SAB Vitality Committee Chair >> >> cell +1-571-274-7901 >> >> annette.reilly@computer.org <mailto:annette.reilly@computer.org> >> >> -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- >> >> >> -- >> This message has been scanned for viruses and >> dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is >> believed to be clean. >> >> >> >> -- >> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> Jim Lewis Jim@SynthWorks.com <mailto:Jim@SynthWorks.com> >> VHDL Training Expert http://www.SynthWorks.com >> IEEE VHDL Working Group Chair >> OSVVM, Chief Architect and Cofounder >> 1-503-590-4787 >> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> >> -- >> This message has been scanned for viruses and >> dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is >> believed to be clean. > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Jim LewisJim@SynthWorks.com > VHDL Training Experthttp://www.SynthWorks.com > IEEE VHDL Working Group Chair > OSVVM, Chief Architect and Cofounder > 1-503-590-4787 > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is > believed to be clean. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-590-4787 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Jan 26 09:06:32 2015
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