Re: [vhdl-200x] Proposal for improved physical types

From: David Koontz <diogratia@gmail.com>
Date: Fri Jan 09 2015 - 21:19:32 PST
On 10/01/2015, at 9:13 am, Tristan Gingold <tgingold@free.fr> wrote:

> On 08/01/15 22:41, Kevin Thibedeau wrote:
> >      type frequency is range 0 to physical'high units
>>       uHz;
>>       milliHz = 1000 uHz;
>>       Hz  = 1000 milliHz;
>>       kHz = 1000 Hz;
>>       MHz = 1000 kHz;
>>       GHz = 1000 MHz;
>>       THz = 1000 GHz; -- Up to 9.2 THz with a 63-bit positive range
>>     end units;
> 
> What is wrong with:
> 
>  type frequency is range 0 to 2**63 -1 units
>     ...
>  end units;
> 
> Should be already supported.

package physical is
    type FREQ is range 0 to 2**63 -1 units  -- line 209
        Hz;
        kHz = 1000 Hz;
        MHz = 1000 kHz;
        GHz = 1000 MHz;
        THz = 1000 GHz;
    end units;

ghdl -a top_physicaltest.vhdl
top_physicaltest.vhdl:209:30: arithmetic overflow in static expression
top_physicaltest.vhdl:209:26: range constraint for a physical type must be static

(ghdl-0.31).

Analyzes successfully with 2**62 -1, and that sounds like an implementation limit.

Looks like there should be an implicit type conversion issue here too, unless universal integer is defined as 64 bit. It's tied to integer and integer is used in index and discrete ranges.  Tristan's example uses something that looks like a universal integer but is out of range for an integer.

VHDL's type system comes from CONLAN, with a base type of univ@.  There is no provision for two different universal integer types in VHDL or CONLAN. 

It'd be a massive change to uncouple universal integer and integer or integer from index and discrete ranges, and the need for bigger user defined Physical types hasn't been demonstrated. 

I'd like to see some strong use cases than something simply contrived and used as justification. I'd imagine synthesis vendors would, too. VHDL is a hardware description language.  The need to do abstract math can be limited to actual hardware.

By the time we need to deal with models that have an index dimensionality too large to fit in 2**31  we'll be dealing with new ways of describing and verifying them or we'll still be using dimensionality and sectioned models for verification because we can't build fast enough simulators (and if we could we wouldn't need to build hardware for most applications anyway).

Predefined physical type Time as a 64 bit value doesn't get bitten because it's declaration isn't visible.  What about Time'POS(X)  for X bigger than  will fit in a universal integer? Clamping to integer'HIGH doesn't sound useful, nor does rollover.  

The ability to test the effects of discrete limits in hardware against real numbers isn't required in a VHDL simulation (the continuum hypothesis raises it's ugly head).  Accuracy is a design issue that should be addressed before modeling. You're supposed to be verifying hardware models not abstract math. , VHDL isn't a general purpose programming language (it simulates too slowly if nothing else).


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Received on Fri Jan 9 21:20:10 2015

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