[vhdl-200x] RE: {Spam?} Re: EXTERNAL: [vhdl-200x] A compromise about modular type, boolean operations, integers...

From: <whygee@f-cpu.org>
Date: Thu Oct 23 2014 - 19:37:44 PDT
Le 2014-10-24 04:14, Jones, Andy D a écrit :
> Tristan,
> 
> How you evaluate an expression is based on precedence. My proposal
> performs the subtype's modulo operation last (only on assignment),
> yours elsewhere/everywhere(?), based on how you described the intended
> result. Neither is more or less correct than the other.
> 
> What do we want? A subtype that is interoperable with its base type
> and subtypes thereof?
> 
> Or do we want types for which we have to redefine the operators for
> every combination of operand and return types we want to support? What
> happens when you want to add a modulo 3 type to a modulo 4 type? What
> is the modulo of the sum?
> 
> In your example, how would you propose communicating to the "+"
> operator that it is supposed to produce a modulo 4 result, given two
> integer literals?

(I remarked the same thing in another post)

> For subtypes, how would you communicate the expected subtype for the
> return value? Be careful, this gets Verilogish (and NOT backward
> compatible with VHDL) very quickly!
> 
> My solution is to not communicate the operand or return subtype to the
> operators at all, but that they always operate on, and return, the
> base type, same as they always have in VHDL, and perform the modulus
> on assignment, the same place bounds checking for subtypes has always
> been.
> 
> Simply replacing bounds-checking behavior with modulo-wrapping
> behavior only makes sense if both are performed the same way, at the
> same place.
> 
> One way to do that is with resolved subtypes, and another way is to
> define "special" subtypes (modulo instead of range).  A special,
> language-defined subtype can only do one thing. A resolved subtype,
> with user-defined resolution functions, suitably extended to
> variables, can do MUCH more.

*nod*

However I don't think I'd need more than modular and saturated,
and being a "bare metal" kind of guy, I don't think I'd want to call
a user function whenever I assign a value...

What is the status of the proposed extension of resolution functions to 
variables,
instead of only signals ?


> Andy D Jones
> Electrical Engineering
> Lockheed Martin Missiles and Fire Control
> Dallas TX
YG

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Received on Thu Oct 23 19:38:05 2014

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