Hi, I have just written a proposal to addresses issues with assigning integer values to unsigned, signed, real literals to ufixed, sfixed, and float, and vice-versa. Obviously with some constraints. You will find it here: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/ImplicitConversionNumeric This borrows thoughts and requirements from: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/FunctionsKnowOutputSubtype http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/OverloadAssignment and observations/frustrations about usage of type integer and real in assignments and expressions. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-590-4787 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Oct 14 12:32:14 2014
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