RE: [vhdl-200x] "??"[std_ulogic return boolean] and meta values

Sounds good to me.  I assume you want the assert condition to be something like

   assert NO_WARNING or ('X' = to_X01(l))

- Ryan

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis
Sent: Tuesday, September 09, 2014 11:09 PM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] "??"[std_ulogic return boolean] and meta values

Hi,
In conjunction with a stack overflow post, http://stackoverflow.com/questions/25737877/how-to-get-simulation-warning-when-comparing-std-logic-with-x, I have been looking at the 'X' handling of overloaded versions of "=" and "??".

If you look at "="[unsigned, unsigned return unsigned], you will note that if one of the inputs has an 'X', an assertion warning is produced.

OTOH, if "??" sees an 'X' it quietly reports false.   From std_logic_1164:
  function "??" (l : STD_ULOGIC) return BOOLEAN is
  begin
    return l = '1' or l = 'H';
  end function "??";

To be consistent with numeric_std, it would seem appropriate that we add an assertion (and NO_WARNING constant) similar to the following:
  function "??" (l : STD_ULOGIC) return BOOLEAN is
  begin
      assert NO_WARNING
        report "STD_LOGIC_1164.""??"": metavalue detected, returning FALSE"
        severity warning;
      return l = '1' or l = 'H';
  end function "??";

What do you think?  Do we need it?  It would slow down code execution.  There would be no backward compatibility issues since it is just an assertion.

Regards,
Jim


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Jim Lewis

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Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder



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