> I don't know what it implies for VHDL implementors but in the end, > this would help reduce the amount of work for future language > revisions > since people would be able to experiment and play, and even actually > use the features that they need for their job, without interfering > with VHDL's philosophy or core principles. I like it :-) But you can do such experiment already today (and even with vhdl 87): declare a record type with one integer element, add declare all the operations you need: +, -, and, or, ... No need to perverse an existing feature to do experimentations. Regards, Tristan. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Aug 3 23:03:58 2014
This archive was generated by hypermail 2.1.8 : Sun Aug 03 2014 - 23:05:46 PDT