Hi David, > And I'll put my opinion out there succinctly. > > If you can't have a 'image attribute that won't operate error free for valid VHDL expressions it doesn't belong in the language. VHDL has no error recovery mechanisms. Why is generating an error message that says that the bounds are out of range of the base type? It does not seem much different from the code below. Cheers, Jim library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.fixed_pkg.all ; entity Ufixed2Unsigned is end Ufixed2Unsigned ; architecture test of Ufixed2Unsigned is signal X: ufixed(4 downto -3) ; signal AX : unsigned(7 downto 0) ; begin X <= "00001111" ; AX <= unsigned(X) ; end test ; -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-320-0782 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jul 23 21:22:13 2014
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