Hi Ryan, > 1. Fundamentally you like the idea and don't see any technical issues with the static approach I suggested. > > 2. You would like to add a facility to globally control the formatting. > > 3. You would like to add a facility to locally override the global formatting controls. > > ... Otherwise, I don't particularly need (2) or (3). The value of 2 and 3 flow out of Tristan's conservative view, "There is no natural format (particular for records)". Fundamentally, I don't know if I prefer parens and commas as you suggest or if I want just spaces between objects, however, if I have 2 and 3, then I can get what I want for a particular situation I am not so worried about writing out in a VHDL-like format, I am more worried about writing out in a format that I can read back in easily. Having to remove the parens and commas on reading is annoying. I prefer "to_string" since it is overloadable ('image is not) and simple to use. Your example took some non-LRM compliant short-cuts. The LRM says that 'image requires "any scalar type or subtype T", and hence, your write statement should be: write(ln, std_logic_vector'image(ary)); OTOH, using to string is just the following. And if I don't like what it does, I can create appropriate overloading for the type. write(ln, to_string(ary)); Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Jul 21 14:54:06 2014
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