Hi Ryan, Did you want 'image or an implicit to_string? Either way, I think it is a solvable problem. Now that we have protected types, we could create global configurations for this sort of thing. The global configuration could define a default composite left brace, composite separator, and composite right brace. Each of these can be strings which would allow them to be either the left parenthesis as you suggest "(" or allow them to be simply separated by spaces " ". Beyond global settings, I would like to support a local override. I have not figured out a pattern for this. The issue I run into is that procedures in a package do not currently have a way to see the context of the calling code. I would also like a write (the built-in one) and writeline that do not require the file specification, but instead write to either a common log file if it is opened or otherwise write to OUTPUT. Again, I potentially see this filtered through a global (standard packge based) shared variable object. Cheers, Jim > All: > > Is there any reason not to create a 'image attribute for composite types (arrays and records)? Right now it only exists for scalar types like integer, real, etc. One possible definition is a paren-enclosed, comma-delimited sequence of the element images from left to right (array) or first-to-last defined (record). I believe this would make X'image a valid VHDL aggregate expression representing the current value of X. It's easy to define, unambiguous, and quite general. > > > Example: > > > process images is > variable ary : std_logic_vector(0 to 3) := b"011"; > variable ln : LINE; > begin > write(ln, ary'image); > writeline(OUTPUT, ln); > end process; > -- Will print "('0','1','1')" according to my suggestion. > > > Thanks! > > --- > Ryan Hinton > L-3 Communications / Communication Systems West > ryan.w.hinton@L-3com.com > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Jul 21 12:18:24 2014
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