> The question is, do we want a new type, with its own, duplicative > infrastructure, or do we want a way to use INTEGERs with an > automatic, modulo behavior? > > Resolved types are one way to achieve the latter. Well, resolution function applies only on signals. > Before we run off and change the language, let's see if we can get > what we want easily enough with the existing language. That's the > VHDL way, not the SystemVerilog way. You can't achieve modulo arithmetic with resolution function. If you write 17 ** 16, you get a value for a modulo type, but a overflow on integer types. Regards, Tristan. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jun 27 12:51:55 2014
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