[vhdl-200x] Configurations

From: Brent Hayhoe <Brent.Hayhoe@Aftonroy.com>
Date: Wed Apr 23 2014 - 14:22:19 PDT
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I came across a problem/feature of the language with regards to configuration 
naming.

I have an FPGA design with multiple RAM instantiations, which in turn are 
generated via the vendors tool set.

As well as generating the RAM model, the tool also generates a configuration for 
the model. Unfortunately, the tool always generates the configuration with the 
name 'Structure_CON' and so as each model is compiled, the configuration is 
successively overwritten.

Now a standard 'entity' primary unit:

<pre>
entity E is
...
end entity E;
</pre>

with a given 'architecture' secondary unit:

<pre>
architecture A of E is
...
end architecture A;
</pre>

allows us to name the unit as an extended name as 'E(A)'

A configuration is specified as:

<pre>
configuration C of E is
...
end configuration C;
</pre>

which is a primary unit and therefore needs a unique name within its library 
structure.

However, its syntax is reminiscent of an architecture and it is bound to an 
entity. It appears to be both a primary and secondary unit, a sort of 1.5 unit.

Mainly in simulations, I call a configuration directly to start a run, which is 
a benefit of being a primary unit. However, it could still be achieved if it 
were a secondary unit accessing it as E(C).

Its not a big issue, but I was wondering if this had ever been discussed before?

Brent.
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-- 

Regards,

         Brent Hayhoe.

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Received on Wed Apr 23 14:22:49 2014

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