RE: EXTERNAL: Re: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

From: Nick Gasson <>
Date: Tue Apr 01 2014 - 01:35:07 PDT
On 31/03/14 18:43, wrote:
> I'm coming at this from the perspective of, "What might we be able to improve in VHDL?"  I am most productive when the language I'm using supports more direct ways to express the algorithm/block diagram in my head.  That's why I got involved with the last VHDL revision: the unconstrained array elements and fixed-point library significantly improve my ability to express my design intent.  So I asked the question, "What is a VHDL-like way to intentionally create a clocked process?"  Syntax option 3 [] is my best answer.  This is a hardware question, so it's valid to ask of a hardware language.

Hi Ryan,

Of the options listed on that page I actually find option 4 is more in 
keeping with the existing language. E.g. contrast this, using the option 
3 syntax:

     process rising clock(clk) is
     synchronous reset(rst)
         q <= '0';
         q <= d;
     end process;

With this, using the option 4 syntax allowing functions in sensitivity 

     process (rising_edge(clk)) is
         if rst = '1' then
             q <= '0';
             q <= d;
         end if;
     end process;

It is only marginally longer but IMO easier to read. And it avoids 
introducing the notions of "clock" and "reset" which are not currently 
part of VHDL as well lots of extra syntactic sugar.

The semantics should be easy to define in terms of the existing "wait 
until" statement. Similar to how the existing sensitivity list maps to 
"wait on".

It should also be easy for synthesis tools to implement as it is 
basically the same as Verilog's @(posedge clk).


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Received on Tue Apr 1 01:35:31 2014

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