RE: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

From: Jakko Verhallen <jakko.verhallen@diasemi.com>
Date: Thu Mar 27 2014 - 12:01:29 PDT
Hi Ryan,

I agree with you, but I have only one remark.
Syntax 1b:
q <= d after 2;
This very much resembles an asynchronous delay like
q <= d after 2 ns;

Although obvious and consistent, this might be confused for an async delay.
Even more, if you want to have 2 cycles delay and a async delay, how do you model that?
q <= d after 2 after 2 ns?

I don't like the @ either, so I would rather vote for something like
q <= d pipe 2 [after 2 ns];

Jakko


From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of ryan.w.hinton@L-3com.com
Sent: Thursday, March 27, 2014 6:54 PM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

I've been meaning to work on this proposal and add my preferences and arguments.  I'll summarize here.

I GREATLY prefer syntax 1b.  What does the @ mean?  Where else is it used in VHDL?  Why are we introducing and reserving a new symbol/operator?  Especially when we already have a reserved keyword "after" whose semantics are exactly what we're trying to add (or at least obvious in context).  It would be fun to add a new physical constant "cycles" or something.  But I assume we won't add that (a) because of English's singular/plural issues, e.g. "after 1 cycles", and (b) because I've heard that compilers have fits if you try to shadow a physical type.  Someone told me once, "Just try to name a signal 'ns' and see what happens!"

In changing an existing, established, mature language like VHDL, I like to make changes as much as possible (1) limited, (2) obvious, and (3) consistent.  Perhaps the '@' symbol would make Verilog people happy.  But as a VHDL user, I find it neither obvious nor consistent (see my first paragraph).  On the other hand, I think 'after' is fairly obvious and consistent.  In fact, the consistency helps make it more obvious.

Now you have my opinion. :-)

- Ryan

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Daniel Kho
Sent: Thursday, March 27, 2014 11:45 AM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

Hello,
For the ClockedShorthand<http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/ClockedShorthand> proposal, it seems that Syntax 1 was generally accepted by most people during previous discussions.
However, Syntax 1 proposed two different syntaxes which serve the same purpose:
Syntax 1a:
q <= d @ 2;
Syntax 1b:
q <= d after 2;
where '2' indicates the number of cycles to delay d before effectively driving q.

I would like to seek your comments on which of the two syntaxes is more favourable, and why?
Or does anyone think that both syntaxes should be supported?

regards, daniel

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Received on Thu Mar 27 12:01:49 2014

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