RE: [vhdl-200x] Switch model

One simple solution to the problem mentioned below with differential transceivers and analogue switches is to simply add the appropriate time delays.  In the situation described below, the 'troubling to model' parts both presumably have datasheets and most likely do not specify a 0 ns propagation delay.  Simply modeling the part with the manufacturer's specified prop delays will avoid having multiple delta cycles be part of the problem.  One could argue (for this case), that adding the delay more properly models the part than 0 ns delay.

I realize that a general solution may be handy as well, but in order to justify the language change one should probably come up with scenarios that don't already have a solution and then see how much support there is for that class of scenarios.

Kevin Jennings, P.E

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Brent Hayhoe
Sent: Monday, March 10, 2014 8:15 PM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Switch model

As I've (re-)started this thread I will generate a proposal for it.

However I think we should leave the discussion on the reflector for now until we 
can sort out these delta cycle propagation problems, especially the problem of 
two switches in a row.

I will have a play with my current test bench and see what happens.

I can second Rick on this problem as I have had many issues in trying to support 
this bidirectional assignment problem in many test bench scenarios before.

My current task involves targeting a commercial development board which has 
differential transceivers (separate from the FPGA) and 'bypass-able' using 
analogue switches. Hence my need to get a solution (which I have at present) for 
my application test bench, but also wanting to generate properly supported VHDL 
functionality for this.

The main task as Jim says is quantifying the problem, but also identifying a 
simulate-able solution for the problem(s).

Cheers,

Brent.

On 10/03/2014 20:36, Jim Lewis wrote:
> Hi Rick,
> Would have been happy to support your detailed proposal for this for 
> VHDL-2008.  However, while people asked for the feature, no one liked it so 
> much that they were willing to volunteer to write it up and make it happen.
>
> I suspect the rest of the working group would have supported this work also if 
> someone who really needed it would have written the proposal.
>
> I would be happy to support it now too.  We need to quantify exactly what we 
> need.
>
> I understand connections of the form:
> A <=> B ;
> A <=> B when S = '1' ;
>
> However, VHDL-2008 had requests for something of the form without any circuit 
> for it.   I have never had a need for this, so this meant to me that I did not 
> understand what was wanted enough to successfully complete a proposal.
> A <=> B when S = '1' else C ;
>
> Can anyone provide a compelling reason (circuit not words) to implement this?
>
> We need a proposal documenting all forms needed and the compelling reason 
> (circuits not words) to implement it.
>
> Jim
>
>> Jim,
>>
>> Pull up the datasheet for a TI SN74CBT3125D.  I have been asking for
>> this since the late 1990s.
>>
>> Rick
>>
>>
>>
>> On 03/10/2014 07:41 PM, Jim Lewis wrote:
>>> HI Jakko,
>>> I would particularly be interested in seeing an example and hardware
>>> picture of something that requires conditional usage of this.
>>>
>>> I would more likely call it a switch or attachment operation. Calling it
>>> an assignment is going to make people want to inject delta cycles -
>>> which is not going to work.
>>>
>>> Jim
>>>
>>>
>>>
>>>> Hi Brent,
>>>>
>>>>
>>>> What you actually want is a bidirectional assignment (for any resolved
>>>> type).
>>>>
>>>> The problem with the code you listed below, is that you cannot have 2
>>>> of those assignments in a row, it will lead to wrong results.
>>>>
>>>> If you could assign 2 ways (like tran or tranif), then the problem is
>>>> solved.
>>>>
>>>> I'd like to see something like
>>>>
>>>> a <=> b [when c else 'Z'];
>>>>
>>>> This would ease multiport wires with bidirectional (and conditional)
>>>> assignments.
>>>>
>>>> Jakko
>>>
>
>


-- 

Regards,

         Brent Hayhoe.

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