HI Jakko, I would particularly be interested in seeing an example and hardware picture of something that requires conditional usage of this. I would more likely call it a switch or attachment operation. Calling it an assignment is going to make people want to inject delta cycles - which is not going to work. Jim > Hi Brent, > > > What you actually want is a bidirectional assignment (for any resolved type). > > The problem with the code you listed below, is that you cannot have 2 of those assignments in a row, it will lead to wrong results. > > If you could assign 2 ways (like tran or tranif), then the problem is solved. > > I'd like to see something like > > a <=> b [when c else 'Z']; > > This would ease multiport wires with bidirectional (and conditional) assignments. > > Jakko -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Mar 10 10:41:15 2014
This archive was generated by hypermail 2.1.8 : Mon Mar 10 2014 - 10:41:48 PDT