Hi, Bugzilla 95 raises concerns about xnor reduction, has been closed and marked as invalid. This is the summary from the January 16th meeting: * Chucks concerns are that: A xnor B xnor C /= xnor(A,B,C). * And for xnor reduction operations, xnor A(2 downto 0) = not xor A(2 downto 0) and is not the same as A(2) xnor A(1) xnor A(0). * If one interprets xnor A(2 downto 0) as a 3 input xnor gate this exactly matches how hardware and Verilog works, and hence, the VHDL-2008 impementation is ok. If you wish to re-open this issue, now is the time to speak up. The bugzilla record is at: https://bugzilla.mentor.com/show_bug.cgi?id=95 Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-320-0782 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 16 14:56:42 2014
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