Hi Jim, I guess that brings up the question if the package itself has been verified and validated carefully and if so what are its limitations in terms of accuracy of results and whether they have been quantified. The associated documentation says: "These algorithms are not exhaustively debugged....use at your own risk..". Besides, I am not sure why I would want to validate a hardware implementation of these functions if I am using pre-verified implementations of these in my overall design which is generally the case in complex designs. I understand that if I do an implementation of my own, then I would like to verify it. But do I really need to verify my implementation this way? If verification is indeed an objective of including such packages, then the documentation should be more rigorous with more insight into how the package code works. The reason I am a bit picky about such parts of packages like these is that it makes me feel that probably VHDL equivalent packages of BLAS, LINPACK etc. would be better. Of course based on how packages are being proposed now, it is possible that we can have packages for statistical calculations and likewise. Regards, Sharad On Wed, Oct 9, 2013 at 10:50 PM, Jim Lewis <Jim@synthworks.com> wrote: > Hi Sharad, > There are certainly more applications than just synthesis. > The most obvious is verification. When you create a hardware > block that implements one of these operations, it is nice > having a package of operators available for independent > validation of the hardware. > > On the other hand, keep in mind that very little in numeric_std > is actually synthesized. Most is guided by pragmas and > metacomments to a particular implementation. As such having > these functions gives users a mechanism to ask their vendors > to implement a particular operation - and hence, provide > a vendor independent way to achieve the functionality. > > Best Regards, > Jim > > Hi group, >> >> I had a look at the Fixed Point Algorithmic User's Guide. I am not >> sure about the utility of including functions to calculate exp(), log() and >> some trigonometric functions like sin(). The reason I >> am not sure is that vendors, at least the FPGA ones, provide IP cores to >> do these operations. Of course they have their own limitations etc. but >> that is another issue. >> >> Is there really a need to include some of those functions in the >> package? If yes, where would they find most utility? Synthesis, testbench >> or both? >> >> Regard, >> Sharad >> >> -- >> This message has been scanned for viruses and >> dangerous content by *MailScanner* <http://www.mailscanner.info/>**, and >> is >> believed to be clean. >> > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~**~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~** > ~~~~~~~~~~~ > Jim Lewis > VHDL Training Expert, SynthWorks > IEEE 1076 VHDL Working Group Chair > Open Source VHDL Verification Methodology (OSVVM), Chief Architect and > Co-founder > > 1-503-320-0782 > Jim@SynthWorks.com > http://www.SynthWorks.com > > VHDL Training on leading-edge, best coding practices for hardware design > and verification. > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~**~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~** > ~~~~~~~~~~~ > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Oct 9 08:21:50 2013
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