Particularly curious as the following is ok: constant MY_SLV : std_logic_vector := "0011" ; signal MySlvSig : std_logic_vector(MY_SLV'range) ; Jim > Is there any reason that constants can get their array range constraints > from initial values, but variables and signals can't? (I believe these > rules are standardized, but I'm looking for the reasoning behind the > standard.) Allowing the latter would make fixed-point design easier. > > Thanks! > > --- > Ryan Hinton > L-3 Communications / Communication Systems West > ryan.w.hinton@L-3com.com > > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-320-0782 Expert VHDL training with a focus on hardware design and test. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Apr 24 10:31:39 2013
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