Re: EXTERNAL: [vhdl-200x] VHDL ternary operation

May I suggest something more general, that provides discussed functionality
and adds more benefits?
Please consider:
   { enum_expression: expr0, expr1, ..., exprn-1 }
*Enum_expression* must be of any enumeration type (maybe even constrained
integral type) - basically speaking any type that has position numbers of
natural type.
The type of *expr0* determines expected type of remaining *expri* and the
resulting type of the entire expression.
Evaluation pattern would be simple:
  1. Evaluate *enum_expression* and compute its position number *i*.
  2. Pick *expri* as the result.

We have to use new symbol to surround the expression. Regular parenthesis
and square brackets are already used, bur curly brackets are not.
With this approach parser would not be confused - it would need new branch.
For boolean expression in the first position, we would get:
    { bool_expression: false_value, true_value }
It would confuse Verilogers, but we don't care about them, do we?

If it is not too complicated, we could even add optional default clause to
support unconstrained select expressions:
   { int_expression: expr0, expr1, ..., exprn, others=>default_value }


Thanks,

Jerry


On Thu, Apr 4, 2013 at 8:08 AM, Jim Lewis <Jim@synthworks.com> wrote:

> Hi Andy,
>
> > If we continue to "cryptify" the VHDL language, we are only accelerating
> its demise.
> I agree.  WRT readability, any of the language
> syntax candidates get ugly quick.
>
> If you use "when" then you have to add parens to
> disambiguate it from the conditional assignment
> form.  While ok for assignments, it would be odd
> requiring it in initializations (such as a constant).
>
> It would also be ugly to have signals and delays
> present.  Such as signal assignments and expressions:
>
> -- signal assignment
> Y <= A after 3 ns when C else B after 4 ns ;
>
> -- Expression
> Y <= (A when C else B) after 4 ns ;
>
> There may be other issues here I am forgetting about.
>
>
> For 2008, we considered the keyword "if" instead of
> "when".  I don't recommend this either.  It may be
> ok if everyone dropped the assignment form with
> "when" and just used "if".  OTOH, if you consider it
> WRT to the simplified conditionals, then one can write:
>
> if (A if C else B) then
>
> Even with the parens it is real ugly.
>
> I would particularly hate to have a cryptic form, such
> as "C ? A : B"
>
>
> As I mentioned before, I would rather have anonymous
> ports on subprograms and a general function for
> multiplexors (we already have requests for small
> logic like this):
>
> if Mux2(C, A, B) then
>
> Perhaps it would be more general named in a software
> sense and named it something like Sel2:
>
> if Sel2(C, A, B) then
>
> The ugly things that can happen here is if a design
> uses Sel2 as a signal name, but that is ok as it is
> taken care of by normal scoping rules.  The only time
> it would be an issue is if the signal is declared in
> a package - which most designs do not do since there
> has been no historical support by synthesis tools.
>
> I like having the size specified in the name as it
> also gives some information about the dimensions of
> the select input.  However, a good argument could
> convince me otherwise.
>
> Jim
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~**~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~**
> ~~~~~~~~~~~
> Jim Lewis
> Director of Training             mailto:Jim@SynthWorks.com
> SynthWorks Design Inc.           http://www.SynthWorks.com
> 1-503-320-0782
>
> Expert VHDL training with a focus on hardware design and test.
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