Re: EXTERNAL: [vhdl-200x] VHDL ternary operation

From: <>
Date: Thu Apr 04 2013 - 09:23:30 PDT
An off-the-wall suggestion.

A <= either B when C or D after 1 ns;
E := (either F when G or H when J or K) + (either (either L when M or N) 
when P or Q );


John A 

From:   Jim Lewis <>
Date:   04/04/2013 16:09
Subject:        Re: EXTERNAL: [vhdl-200x] VHDL ternary operation
Sent by:

Hi Andy,
 > If we continue to "cryptify" the VHDL language, we are only 
accelerating its demise.
I agree.  WRT readability, any of the language
syntax candidates get ugly quick.

If you use "when" then you have to add parens to
disambiguate it from the conditional assignment
form.  While ok for assignments, it would be odd
requiring it in initializations (such as a constant).

It would also be ugly to have signals and delays
present.  Such as signal assignments and expressions:

-- signal assignment
Y <= A after 3 ns when C else B after 4 ns ;

-- Expression
Y <= (A when C else B) after 4 ns ;

There may be other issues here I am forgetting about.

For 2008, we considered the keyword "if" instead of
"when".  I don't recommend this either.  It may be
ok if everyone dropped the assignment form with
"when" and just used "if".  OTOH, if you consider it
WRT to the simplified conditionals, then one can write:

if (A if C else B) then

Even with the parens it is real ugly.

I would particularly hate to have a cryptic form, such
as "C ? A : B"

As I mentioned before, I would rather have anonymous
ports on subprograms and a general function for
multiplexors (we already have requests for small
logic like this):

if Mux2(C, A, B) then

Perhaps it would be more general named in a software
sense and named it something like Sel2:

if Sel2(C, A, B) then

The ugly things that can happen here is if a design
uses Sel2 as a signal name, but that is ok as it is
taken care of by normal scoping rules.  The only time
it would be an issue is if the signal is declared in
a package - which most designs do not do since there
has been no historical support by synthesis tools.

I like having the size specified in the name as it
also gives some information about the dimensions of
the select input.  However, a good argument could
convince me otherwise.

Jim Lewis
Director of Training   
SynthWorks Design Inc. 

Expert VHDL training with a focus on hardware design and test.

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Received on Thu Apr 4 09:24:23 2013

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