Brent, Right now 6.5.6.3 explicitly forbids the use of 'inertial' in actuals associated with anything but ports in port maps. In addition, 4.2.2.1 says that actual associated with formal parameter of signal class must be a signal name. If we carry the trick of "creating anonymous intermediate signal for expression association" from port to signal parameters, it should be relatively easy to implement. It would be nice to hear from tool vendors if they are aware of any hidden issues of adding this feature. Jerry On Wed, Feb 13, 2013 at 12:55 PM, Brent Hayhoe <Brent.Hayhoe@aftonroy.com>wrote: > Thanks for that Jerry, > > Yet another 2008 enhancement that passed me by! > > Now, as far as I understand it, this applies only to port clauses of > entities and block port maps. > > Do you think that we would be able to extend this to parameter clauses of > procedures with signal ports? > > Brent. > > > On 13/02/2013 00:31, Jerry Kaczynski wrote: > >> Brent, >> >> VHDL 2008 did it a little bit differently: it allows expression preceded >> by 'inertial' keyword as the actual associated with input port formal in a >> port map. >> Such association implies the use of anonymous signal to which the >> expression value is assigned concurrently; the anonymous signal is them >> mapped to the formal port. >> So you can write: >> P => inertial A and B >> which will be translated internally to: >> -- outside the instantiation >> anonymous <= A and B; >> -- within port map >> P => anonymous >> The big bonus is that in case of non-static expression being mapped to >> port, 'inertial' is automatically assumed, so you can, but do not have to >> write it. >> So in our case - if P is bit input port and A and B are bit signals - you >> can write: >> P => A and B >> and it will still create that anonymous intermediate signal and >> concurrent assignment to it. >> Of course in both cases one delta cycle is added during simulation due to >> the concurrent assignment to the signal. >> If you have access to the 2008 standard, everything is described in >> clause 6.5.6.3. >> >> Thank you, >> >> Jerry Kaczynski >> Aldec research Engineer >> >> >> On Tue, Feb 12, 2013 at 3:27 PM, Brent Hayhoe <Brent.Hayhoe@aftonroy.com<mailto: >> Brent.Hayhoe@aftonroy.**com <Brent.Hayhoe@aftonroy.com>>> wrote: >> >> Whilst scavenging through some of the older reflector Emails, I >> stumbled >> upon Jim's original 'wish list' document for the VHDL2008 (eventual) >> fast >> track stuff: >> >> http://www.eda-twiki.org/vhdl-200x/**docs/jims_200x_requests.pdf<http://www.eda-twiki.org/vhdl-200x/docs/jims_200x_requests.pdf> >> >> In section 10.1, I saw: >> >> Y => signal'(A and B), >> >> for a port mapping and thought what a nice idea. >> >> Does anyone know if this was pursued/rejected, and if not/so then >> why-not/why? >> >> >> -- >> Regards, >> >> Brent Hayhoe. >> >> > -- > > Regards, > > Brent Hayhoe. > > Aftonroy Limited Telephone: +44 (0)20-8449-1852 > 135 Lancaster Road, > New Barnet, Mobile: +44 (0)79-6647-2574 > Herts., EN4 8AJ, U.K. Email: > Brent.Hayhoe@Aftonroy.com > > Registered Number: 1744190 England. > Registered Office: > > 4th Floor, Imperial House, > 15 Kingsway, > London, WC2B 6UN, U.K. > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Feb 13 13:39:20 2013
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