RE: [vhdl-200x] RFC: std.textio.OUTPUT ?

I use TEXTIO a bit.   In fact one method I teach is that your reference model output results into a file for test transactions to
help verify the RTL version that will be input into synthesis.   
For most, I use files that have simple sequential access and it works great.

I seldom use STD_INPUT or STD_OUTPUT.

JD

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Martin.J Thompson
Sent: Wednesday, January 23, 2013 8:00 AM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] RFC: std.textio.OUTPUT ?

> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On 
> Behalf Of Walter Gallegos
> Sent: 23 January 2013 12:22
> To: vhdl-200x@eda.org
> Subject: Re: [vhdl-200x] RFC: std.textio.OUTPUT ?
> 
> So, when simulation start, I like an empty transcription window or 
> file; thinking the transcription windows and files as views of the 
> stream model; WRITE_MODE do exactly that.
[MJT] 

Do simulators behave like that?  None in my experience clear the transcript window at the start of a simulation.

Cheers,
Martin

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