Re: [vhdl-200x] Support for Register Address Descriptors: Was: Support for hex, ....

All,

Re SystemVerilog and UVM, SystemVerilog has nothing to say about register description files. The UVM Register Layer (aka uvm_reg) is an SV class library for  creating a model of the registers in a design. The UVM register layer explicitly DOES NOT  standardize the description of the system memory map: rather UVM expects tools providers to offer generates to create the UVM register model from an address map in some other format. SystemRDL would be one candidate amongst several.

Re SystemRDL, to quote the ASI web site directly:

<quote>
In May 2009, The SPIRIT Consortium announced the release of the  SystemRDL specification. SystemRDL is a language for the design and  delivery of registers to be used in IP blocks within electronic designs.  The SystemRDL 1.0 Standard was transferred to Accellera upon the merger  of The SPIRIT Consortium with Accellera Organization in 2010.
 Shortly after Accellera merged with the Open SystemC Initiative  (OSCI) in late 2011 to become Accellera Systems Initiative, the board of  directors formed a new working group to focus on the next revision of  SystemRDL. The new SystemRDL Working Group commences work in the Fall of  2012 and is actively seeking members.
</quote>


Cheers,

John A


-----owner-vhdl-200x@eda.org wrote: -----
To: vhdl-200x@eda.org
From: Srinivasan Venkataramanan 
Sent by: owner-vhdl-200x@eda.org
Date: 12/20/2012 04:44PM
Cc: Jim Lewis <Jim@synthworks.com>
Subject: Re: [vhdl-200x] Support for Register Address Descriptors: Was: Support for hex, ....

Hans,
  By any chance you meant to write:

>> I assume you mean something like SystemRDL wh

instead of:

>> I assume you don't mean something like SystemRDL
 
B'cos that's kind of a relevant link. Though IP-XACT has become more accepted standard for this. Jim - Yes SV/UVM has something called "UVM Registers" for this very purpose. 

Thanks
 Srini
www.cvcblr.com/blog 


On Thu, Dec 20, 2012 at 9:27 PM, ht-lab <hans64@ht-lab.com> wrote:
 Hi Jim,
 
 I assume you don't mean something like SystemRDL which was donated to Accellera some time ago.
 
 Regards,
 Hans.

 
 On 20/12/2012 15:07, Jim Lewis wrote:
  Hi All,
 What I would really like to see for this is a common
 descriptor file that defines the address, number of
 bits, and read/write capability of a register that
 can then be processed into a ".h" file for c programmers
 and one or more packages for the VHDL development team.
 
 In addition, with the right sort of information in the
 packages, it would seem that the testing of our
 register space of our design should be able to be
 handled in a standardized way.
 
 I am fairly certain SystemVerilog has done something
 like this.  It would be nice to have a corresponding
 capability for VHDL.
 
 Best,
 Jim
 
  Hello,
 
 currently VHDL doesn't seem to support a construct which allows the usage of hex numbers instead of integer numbers. For example sometimes I encode my addresses like this:
 
 CONSTANT
     C_ADDRESS_WIDTH
         : integer := 4;
 
 CONSTANT
     C_READ_DATA
         : unsigned(C_ADDRESS_WIDTH - 1 DOWNTO 0) := to_unsigned(1, C_ADDRESS_WIDTH);
 
 it would be nice if I could write it like this or something similar:
 
 CONSTANT
     C_ADDRESS_WIDTH
         : integer := 12;
 
 CONSTANT
     C_READ_DATA
         : unsigned(C_ADDRESS_WIDTH - 1 DOWNTO 0) := to_unsigned(0x1, C_ADDRESS_WIDTH);
 
 This way if I have to adjust the address width there would be just one position in the code which I would have to modify. The hexadecimal coding would be more in line with the address encoding the microcontroller programmers use. Other suggestions would be welcomed though.
  
 
 Best regards
 i.A. Martin Stolpe
 
 
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