RE: [vhdl-200x] Records with diectional subtypes

I vote for using OPEN or NULL or something. Port/parameter maps have a
default mode of IN if not otherwise specified.

- Ryan

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Peter Flake
Sent: Sunday, August 19, 2012 3:16 AM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Records with diectional subtypes

Hi Jim,

I am not sure whether it better to use the "open" keyword, or simply to
omit the signal from the direction list. It creates a new syntactic
category to have "open" as an alternative to in, out, inout. But it
does make it clearer if all the signals must be listed.

Regards,

Peter.

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jim Lewis
Sent: 16 August 2012 21:08
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Records with diectional subtypes

Hi Peter,
In the Block Interface proposal, "Candidate: Records with diectional
subtypes":
http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/BlockInterfaces#Candidate_Re
cord
s_with_direction

Can we extend this to also allow open in the subtype? The following
slave does not use the "we" element (perhaps it is read only and never
does a
write):

subtype t_slave is t_cpu_bus port(adr, dat, en : in; sdt, ack, err :
out; we : open);

Can we allow some ports to not use all elements?

type t_cpu_bus is record
     adr : std_logic_vector(15 downto 0); --Address
     dat : std_logic_vector(15 downto 0); --Data from master to slave=
     we : std_logic; --Write enable from master=
     en : std_logic_(7 downto 0) ; --Enable from master=
     sdt : std_logic_vector(15 downto 0); --Data from slave to master=
     ack : std_logic; --Acknowledge from slave=
     err : std_logic; --Error from slave= end record;

subtype t_master is t_cpu_bus port(adr, dat, we, en : out; sdt, ack, err
:
in);

subtype t_slave is t_cpu_bus port(adr, dat, we, en(1) : in; sdt, ack,
err :
out ; en(7 downto 2), en(0) : open );

  Inside the slave is en seen as en(1) or just en? Is there a notation
that allows just en?

All questions also on the twiki page.

Best,
Jim

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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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