Re: {Disarmed} Re: [vhdl-200x] Directional records proposal

On 8/1/2012 2:07 PM, Brent Hayhoe wrote:
> Hi Ryan,
> In-line again I think:
> On 23/07/2012 14:26, ryan.w.hinton@L-3com.com wrote:
>>
>> No problem about the telecon, just trying to relay some of the
>> discussion.
>>
>> I'll reply inline below to a few of your comments. Some I'll address in
>> a reply to Andy's comments.
>>
>> > From: owner-vhdl-200x@eda.org [_mailto:owner-vhdl-200x@eda.org_
> <javascript:popup_imp('/imp/compose.php',700,650,'to=owner-vhdl-200x%40eda.org');>]
> On Behalf
>> > Of Brent Hayhoe
>> > Sent: Sunday, July 22, 2012 12:49 PM
>> > To: vhdl-200x@eda.org
>> > Subject: Re: [vhdl-200x] Directional records proposal
>> >
>> > Hi Ryan,
>> >
>> > Firstly, I apologize for not taking part in the teleconference but
>> > unfortunately my work situation precludes it.
>> >
>> > My comments are embedded below:
>> >
>> > On 19/07/2012 19:23, ryan.w.hinton@L-3com.com wrote:
>> > >
>> > > Brent:
>> > >
>> > > This seems a complicated way to do something simple. By breaking
>> the signals
>> > > out of the record, no new syntax is required. But I think the
>> point of your
>> > > suggestion is to allow keeping all the signals in one record.
>> > >
>> > I'd rather think of this as a simple example to show complex
>> functionality.
>> > Breaking signals out of the record is the only option that has
>> been available
>> > since day 1. Keeping the record intact through port structures
>> (and providing
>> > directional capability) would enable top level simplified structural
>> > interconnect and in so doing make the need for 'block diagramming'
>> tools less
>> > important (a pet hate of mine).
>> >
>> Part of evaluating a new language feature is seeing how it might be
>> accomplished with existing features. I agree that having one port would
>> be nice. But how nice? This is the "benefit" part of the equation.
>> And that's why I called it "icing" -- because all the uses I've seen so
>> far can be accomplished with a pair of records, one IN and one OUT.
>> Please don't misunderstand: I like the feature! But I'm having a hard
>> time swallowing some of the proposed syntax and related extensions --
>> the "cost" part of the equation.
> This is a direct problem for the top level structure. The problem I
> encounter time
> and again is that VHDL structure, particularly at a device top level,
> is seen to
> be too complicated. Often the solution to this is to mandate schematic
> entry tools
> for top level design, which inevitably moves the source control from
> VHDL to the
> schematic tool's proprietary data file format.
Yup, sometimes just a binary blob.

> Records have the ability to simplify the structure. The (necessary)
> complexity is
> in the declaration (component) structure which can be hidden from the
> top level
> code by declaring it within a package. The solution of using record
> pairs doubles
> the complexity and in more cases than I care to remember, has led to
> record
> structure usage (within RTL designs) being abandoned completely by
> engineers.
> The existing solution of using pairs of records is, in my opinion, a
> necessary
> bodge due to the lack of support for record types in the first place.
> The record
> type itself is just a bundle, a conduit, a composite set of varied
> types. It has
> nothing to do with directionality and should have nothing to do with
> it. The
> logical place for I/O declarations is at the entity/component level (+
> procedures)
> and maintains visibility of this for the compiler and more importantly
> the coder
> at this level. Top level structure needs to be about interconnectivity
> and not
> I/O structure.
Indeed.
> This has always been handled within the blocks themselves.

Yes, *inside* the box -- not at the edge.

    -- Mike Treseler

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