Daniel,
> <quote>Still, VHDL /= std_ulogic</quote>
> Yes, that's why I mentioned the use of type casting and type conversions to reduce them to std_ulogics.
> For scalar types that make sense as a bus signal, for example, integers, we can use conversion functions to reduce them to bits.
If your solution cannot embrace integers as integers,
then I would consider it invalid.
Stop trying to solve the resolution function issue.
It is adequately addressed by using resolved elements
in records. I have been using record IO with resolved
elements for 16+ years. This includes using
integer, real, and time - this is a VHDL-87 type feature.
Please construct some test cases so you understand this
issue.
Having separate IO modes for each element of a record
that is resolved a the record level will make handling
them by tools more complicated than can be justified
considering that there is a simple way to handle it -
by requiring that any record field that has an inout
mode be a resolved element.
Best Regards,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Received on Thu Jul 19 07:45:12 2012
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