Re: [vhdl-200x] Associative arrays

From: Jim Lewis <>
Date: Wed May 30 2012 - 23:03:55 PDT

Hi Martin,
> I'm taking a look at implementing an associative array in VHDL - which raises a number of questions about the fundamental requirements, and some on possible APIs.
> Requirements questions
> ================
> 1) Is it important that the accesses be ordered (so you can iterate over the key, value pairs in a consistent order every time)? For example, Python's (and I think Perl's) dictionaries are
> unordered. C++ std::map is ordered, std::hash_map is unordered.
> ...

I think the method interface is more important than the implementation.
One of the things that we have seen a need for with some of the packages
David Bishop is working on is named packages that are selectable on a
design unit by design unit basis.

Perhaps we need the same type of capability with protected types.
That way we could have an ordered and non-ordered implementation
that could be selectable by selecting the PT body some how. It
is a good time to think about this as I am also thinking we need
generics for protected types and I would want the two capabilities
to play nicely with each other.

If we had this, then we could have a body that does unordered lists
and one that does ordered lists.

> What should the API look like?
> ====================
> ...
> Serialisation
> --------------
> Would we like to be able to serialise this (and other) new data-types we create?
> a.write(file)
Yet another use model that supports the need for PTs to
allow file identifiers as a parameter.

What do other languages do?

I am adding the Verilog VMEM format for my memory model.


Jim Lewis
Director of Training   
SynthWorks Design Inc. 
Expert VHDL Training for Hardware Design and Verification
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Received on Wed May 30 23:04:11 2012

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