Re: [vhdl-200x] Clocked Shorthand for Sequencing Testbench Assertions?

Hi Srini,
Thanks for your explanations on PSL and SVA.
These are the kinds of comments that would get me interested in picking up
something which I would otherwise be reluctant to learn.

Looking at how simple your PSL example is below, makes me feel that
learning PSL might not be such a bad idea after all. ;)

Have a nice day!

regards, daniel

On Tue, Mar 13, 2012 at 8:03 PM, Srinivasan Venkataramanan <
svenka3@gmail.com> wrote:

> Hi Daniel,
> As Jim has mentioned PSL is the right answer for this. Infact
> VHDL-08 has PSL incorporated into it, so it is no longer an "external
> language" to VHDL. It can be embedded as comments till all vendors
> support it as part of VHDL-08, though it must be simple - as most of
> them do support PSL anyway.
>
> Most of the capabilities you see in SVA are originally derived from
> PSL. Infact SVA-2009 added more PSL like "LTL" flavor to SVA, so in
> that sense PSL is more mature for VHDL designs (and you don't need
> multiple language expertise, multi-lingual license etc.).
>
> Now coming to syntax/semantics:
>
> SVA:
>
> > sequence s
> >
> > d ##[1:3] e ##1 f;
> > endsequence;
>
> PSL
>
> sequence s1 is {d ; [0 to 2] ; e ; f ;
>
> (Isn't that simpler? :-) )
>
> On PSL reading, you may see:
>
> http://www.project-veripage.com/psl_tutorial_3.php
>
> And of-course our PSL book @ http://www.systemverilog.us/psl_info.html
>
> Feel free to contact us offline on PSL-aware tools/capabilities via
> info@cvcblr.com
>
> Warm Regards
> Srini
> www.cvcblr.com
>
> On Tue, Mar 13, 2012 at 8:35 AM, Daniel Kho <daniel.kho@gmail.com> wrote:
> > Hi Jim,
> > Yes, that syntax is for property / sequence assertions. That expression
> can
> > be defined as a sequence in SV, then used in assertions, i.e. the
> assertion
> > will check if the sequence really took place.
> > Not sure of the exact SV syntax, but might look like this:
> > sequence s
> >
> > d ##[1:3] e ##1 f;
> > endsequence;
> >
> > assert s;
> >
> > Thanks for pointing me to PSL. To be frank, I've never used PSL or VHPI
> or
> > other techniques that require interfacing to an external language.
> > That said, I'll still be taking a good look into PSL as this can be
> directly
> > embedded into VHDL code. Are there any benefits in picking up PSL?
> >
> > I heard some tools are also able to generate hardware descriptions from
> PSL,
> > does anyone know which vendor / tool is capable of doing this? Please
> email
> > me in private as it might not be appropriate to discuss specific vendor
> > tools on the reflector.
> >
> > regards, daniel
> >
> >
> > On Tue, Mar 13, 2012 at 12:24 AM, Jim Lewis <Jim@synthworks.com> wrote:
> >>
> >> Hi Daniel,
> >> That syntax is for assertions right? Are they
> >> using it for testbench sequencing or randomizing
> >> anything too?
> >>
> >> The corresponding syntax for VHDL would be PSL in
> >> the VHDL flavor.
> >>
> >>
> >> > I'm still new to advanced VHDL verification techniques
> >> You will probably need to read one of the PSL books.
> >>
> >> Best,
> >> Jim
> >>
> >>> Hi all,
> >>> I updated the Clocked Shorthand Wiki page with a question on whether
> it's
> >>> currently possible to do VHDL testbench sequencing for property
> assertions,
> >>> similar to what's been done in SV?
> >>> For example, the SV sequence:
> >>> d ##[1:3] e ##1 f;
> >>>
> >>> could perhaps follow the same clocked shorthand notation being
> currently
> >>> proposed? For example, the above sequence could be written as follows
> in
> >>> VHDL:
> >>> seq := d, e @ (1 to 3), f @1;
> >>>
> >>> I'm still new to advanced VHDL verification techniques, so let me know
> if
> >>> there is a compact way of defining test sequences using existing VHDL
> >>> techniques.
> >>>
> >>> regards, daniel
> >>>
> >>> --
> >>> This message has been scanned for viruses and
> >>> dangerous content by *MailScanner* <http://www.mailscanner.info/>,
> and is
> >>> believed to be clean.
> >>
> >>
> >>
> >> --
> >> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >> Jim Lewis
> >> Director of Training mailto:Jim@SynthWorks.com
> >> SynthWorks Design Inc. http://www.SynthWorks.com
> >> 1-503-590-4787
> >>
> >> Expert VHDL Training for Hardware Design and Verification
> >> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>
> >> --
> >> This message has been scanned for viruses and
> >> dangerous content by MailScanner, and is
> >> believed to be clean.
> >
> >
> > --
> > This message has been scanned for viruses and
> > dangerous content by MailScanner, and is
> > believed to be clean.
>
> --
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.
>
>

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.