RE: [vhdl-200x] Parallel execution of procedures within sequentiel statements

From: Joanne Degroat <degroat@ece.osu.edu>
Date: Thu Feb 16 2012 - 10:29:50 PST

Martin,
     I would like to point out that VHDL is an inherently parallel language.
I have just been teaching that to my current HDL class. You can access the
class
slides at ece.osu.edu/~degroat/ece762_web_page.htm and the ones you would
want to look at
are the ones on Timing and Concurrency. You can also contact me directly
at degroat.1@osu.edu

Joanne

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Jim Lewis
Sent: Thursday, February 16, 2012 12:45 PM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Parallel execution of procedures within sequentiel
statements

Reply from Martin Stolpe
--------------------
Hi,

thanks a lot for your replies so far!

Jerry, this is some really nice example you have attached! This example doe=
s even more than what I was thinking of. I just wanted to start the threads=
  but I wasn't sure how the joining of the threads should look like. The
pos= sibility to wait on either one thread to finish or to wait for all
threads = to finish is really great.

The idea in my mind was rather vague. I'm currently working on a testbench =
which should check the startup behavior of a component. There a several han=
dshakes which are running in parallel and which I wanted to test. So the se=
quential behavior of the component looks like this:

1. test reset behavior

2. set several registers in parallel: for that I wanted to use proced=
ures which implement the signal pattern needed for transferring the data; t=
he pattern is the same for all registers

3. send another configuration or more to the registers used in 2.
As the patterns are the same for all the registers it seemed logical to use=
  procedures for that. But as the procedures are using wait statements I
was= n't able to use them in the process because they need to be executed in
par= allel.

So the question is: is there a good way to implement this using the current=
  VHDL standard (then the discussion should be switched to one of the other
= mailing lists mentioned), or is this something which is worth to be
thought=
  about for the next revision of the VHDL standard?

Best regards

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Received on Thu Feb 16 10:30:38 2012

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