On 26/08/2011, at 3:15 AM, David Smith wrote:
> VHDL blissfully ignores the concept of files in the language. Doing file inclusion opens a can of worms here. Is there really a requirement to now add the concept of file inclusion into a language that has no concept of it?
We're also dealing with fractional design units (collections of lexical elements) being conditionally included or excluded to form a complete design unit, which also breaks the same paradigm. I think preprocessors might involve a certain test of faith to begin with.
If you look at Chuck's Bugzilla VHDL-200x item 289 proposing library clauses found in context declarations referenced by context references be deferred as inferred happens to use clauses in 12.4 paragraph 12, context references could be treated as text fragments as well.
The distinction between a context reference and some arbitrary included text is that the former is declared by a context declaration, and is a primary unit. Conditional text doesn't seem to have that luxury because it is intended to be fine grained arbitrary collections of lexical elements.
We're basically struggling with language here to the point it can seem easier to change implementation approaches rather that describe something in the LRM. An easy fallback to avoid files might be to specify an external preprocessor which unfortunately still runs in to the inference that a design file is read and can contain one or more design units.
This is where the idea of a design description came from which is used to derive one or more design units from a design file by potentially using conditional text. By definition file operations are implementation dependent and analysis is intended to involve (complete) design units.
In the case of file inclusion versus inline text you'd be allowing multiple methods to describe (declare) arbitrary linear arrays of lexical elements both indirectly by implementation defined means and directly inline.
The question should be does this indirect declaration method have value?
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