Re: [vhdl-200x] conditional compilation proposal

On 17/08/2011 01:40, Scott Thibault wrote:
> For such a small function, I think a declaration generate would be
> appropriate:
>
> if defined("__EDA_VENDOR_1__") generate
> function real _ID23() is
> begin
> -- vendor 1 version
> end;

Ok, you're taking about defining a new generate statement, which wasn't
clear to me. This new generate works in a declarative region, which is
clearly a problem, and would have to be in addition to a new sequential
generate, to work in sequential regions.

If we ignore the issue of a "declarative generate", The LRM defines
"generate" as providing a "mechanism for iterative or conditional
elaboration of a portion of a description", where elaboration is
"defined for design hierarchies, declarative parts, statement parts
(containing concurrent statements), and concurrent statements" [and
declarations]. An immediate problem is that you're now defining
elaboration in the context of arbitrary sequential statements, which is
not, I believe, a logical or valid thing to do.

If you don't mind me saying so, I believe that you're conflating two
issues here. You (and various others) are using 'generate' as a
shorthand for a language construct that tests a static expression, which
isn't its purpose. The language is already full of requirements for
static expressions, and you're also defining a new one with
"defined(__EDA_VENDOR_1__)". In other words, the "generate" in your
example is redundant anyway; the new "if defined" does the job. Your "if
defined" is, in fact, equivalent to D's static if, which I've already
mentioned elsewhere. The D version has the advantage that it doesn't
introduce a new scope.

Even with a new static if, we still have the obvious issue that the code
is actually analysed and must be valid. The static if would also have to
be defined to have as wide a scope as possible. It's useless if it's
just defined a sequential statement, for example, even if it's combined
with a concurrent generate.

-Evan

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