Re: [vhdl-200x] Marketing Surveys are prohibited by IEEE

I've replied to Daniel privately off this reflector.

John A

From:
Daniel Kho <daniel.kho@gmail.com>
To:
vhdl-200x@eda.org
Cc:
owner-vhdl-200x@eda.org, "Bailey, Stephen" <stephen_bailey@mentor.com>
Date:
27/04/2011 14:00
Subject:
Re: [vhdl-200x] Marketing Surveys are prohibited by IEEE
Sent by:
owner-vhdl-200x@eda.org

Hi John,
This is interesting to know. Are these people working exclusively with SV
designers, or do they also work with VHDL designers?
I for one (I'm not too sure about others) have worked only with VHDL
people, and haven't heard of anyone using SystemC. I know people who use
SV for verification though.

Anyway, I know people now tend to use high-level synthesis languages (like
SystemC) to design hardware, and this is another layer of abstraction
higher than the underlying hardware description languages. From the
organisations I've been, they have separate software teams that do these
things. Yes, they call it the Software/Firmware team, because they program
in C (or SystemC). Current FPGA companies do have their own C compilers
that are used by software developers to design certain applications in C.
I believe the same applies to the ASIC world, where SystemC is being used.
Basically, the C compilers will compile the C sources to HDLs, which are
then re-compiled by the HDL synthesis tools.

Well, I don't really mind working with these people (software engineers).
As designs get larger and more complex, there is a need for both software
engineers (working on C and HLS tools), and also hardware designers using
native HDL. There will be some critical blocks (high-speed blocks for
example) that must be designed directly using HDL, while there are other
blocks which would be more cost-effectively and more feasibly designed by
software engineers (simply because they do not have too stringent
performance requirements, and those blocks would take too much effort if
designed using native HDL).

Also, from my perspective, software engineers tend to use the same HLS
tools for design and verification of their firmware blocks (which gets
synthesised to hardware in the end). And, hardware designers prefer to use
the same language for design and verification of their hardware blocks
(just my opinion). I believe this is the current state of the industry
right now. At least, for the few places I've been, I notice hardware
designers tend to use the same tools and language to do their work; same
story with the software designers.

So, my point is that while the usage trend for HLS tools like SystemC
"seems" to be on the rise, this does not mean hardware engineers will lose
their jobs. Modern designs currently require both disciplines to be
successful in the market.

Regards,
Daniel

On Wed, Apr 27, 2011 at 7:07 PM, <john.aynsley@doulos.com> wrote:
Daniel,

Just for your info, use of SystemC, Vera, and "e" is widespread (I meet
these people on a regular basis, as I know do other people on this
reflector). You don't hear so much about Vera and "e" jobs because their
use tends (as a generalization) to be on legacy projects rather than new
adoption.

Cheers,

John A

From:
Daniel Kho <daniel.kho@gmail.com>
To:
vhdl-200x@eda.org
Cc:
"Bailey, Stephen" <stephen_bailey@mentor.com>
Date:
27/04/2011 11:31
Subject:
Re: [vhdl-200x] Marketing Surveys are prohibited by IEEE
Sent by:
owner-vhdl-200x@eda.org

Hi all,
Just for the record:
"Meanwhile, I'd still like to find out how 16% of respondents claimed to
be using SystemC as a "verification language"; why I've never met any of
these people; why 8% of verification engineers are still using Vera; why I
don't know anyone who's still using Vera and why I haven't seen any Vera
job postings for years"

I too haven't met a single person using SystemC or Vera or "e". And I
thought if the claims that UVM (or OVM or whatever) was so widespread in
use, I am still wondering why I haven't been exposed to these in my
current and previous employments, when I too had to do some level of
verification? Well, just my thoughts.

Regards,
Daniel

On Wed, Apr 27, 2011 at 6:14 PM, Evan Lavelle <eml-vhdl-200x@cyconix.com>
wrote:
On 27/04/2011 00:29, Bailey, Stephen wrote:
Evan, you are just being insulting now. How can you make such
accusations without having no information on the methodology used?

Well, it certainly wasn't intended to be insulting; my apologies to anyone
who was offended. In answer to your question, my comments were made
precisely because the data was presented without any information on the
methodology.

One of the things I actually get paid for is data analysis, and I spend a
fair amount of time separating "fact" from "statistics". I am fully
prepared to accept that Mentor has no axe to grind, and has done the rest
of us a service by sharing the results of this survey, but that doesn't
mean that the results can be taken at face value, any more than for any
other data collection exercise.

Dennis has posted an interesting link. I haven't had the time to look at
this in detail, but the first thing that's obvious, and important, is that
47% of the respondents described themselves as "non-FPGA verification
engineers", and 14% as "FPGA verification engineers". It seems to me that
this might conceivably seriously skew any interpretation of overall
language usage.

I couldn't actually find your data in the blog posts - have I missed
something? As far as I can make out, Harry Foster hasn't yet published the
language statistics, and the figures you gave are from Wally Rhines' DVCON
chart, which you've described as "languages used in verification". You do
also say, for VHDL, "16% projected this year", but it wasn't obvious to me
that all the other figures on the right, which I'd taken to be current
usage, are actually (according to the chart) "next 12 months" projections.

It'll be interesting to get Harry's take on the figures when he's done.
Meanwhile, I'd still like to find out how 16% of respondents claimed to be
using SystemC as a "verification language"; why I've never met any of
these people; why 8% of verification engineers are still using Vera; why I
don't know anyone who's still using Vera and why I haven't seen any Vera
job postings for years; what actually qualifies as "SystemVerilog" usage;
where the "next 12 months" projections come from; and so on.

-Evan

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