Re: [vhdl-200x] Marketing Surveys are prohibited by IEEE

Hi all,
Just for the record:
"Meanwhile, I'd still like to find out how 16% of respondents claimed to be
using SystemC as a "verification language"; why I've never met any of these
people; why 8% of verification engineers are still using Vera; why I don't
know anyone who's still using Vera and why I haven't seen any Vera job
postings for years"

I too haven't met a single person using SystemC or Vera or "e". And I
thought if the claims that UVM (or OVM or whatever) was so widespread in
use, I am still wondering why I haven't been exposed to these in my current
and previous employments, when I too had to do some level of verification?
Well, just my thoughts.

Regards,
Daniel

On Wed, Apr 27, 2011 at 6:14 PM, Evan Lavelle <eml-vhdl-200x@cyconix.com>wrote:

> On 27/04/2011 00:29, Bailey, Stephen wrote:
>
>> Evan, you are just being insulting now. How can you make such
>> accusations without having no information on the methodology used?
>>
>
> Well, it certainly wasn't intended to be insulting; my apologies to anyone
> who was offended. In answer to your question, my comments were made
> precisely because the data was presented without any information on the
> methodology.
>
> One of the things I actually get paid for is data analysis, and I spend a
> fair amount of time separating "fact" from "statistics". I am fully prepared
> to accept that Mentor has no axe to grind, and has done the rest of us a
> service by sharing the results of this survey, but that doesn't mean that
> the results can be taken at face value, any more than for any other data
> collection exercise.
>
> Dennis has posted an interesting link. I haven't had the time to look at
> this in detail, but the first thing that's obvious, and important, is that
> 47% of the respondents described themselves as "non-FPGA verification
> engineers", and 14% as "FPGA verification engineers". It seems to me that
> this might conceivably seriously skew any interpretation of overall language
> usage.
>
> I couldn't actually find your data in the blog posts - have I missed
> something? As far as I can make out, Harry Foster hasn't yet published the
> language statistics, and the figures you gave are from Wally Rhines' DVCON
> chart, which you've described as "languages used in verification". You do
> also say, for VHDL, "16% projected this year", but it wasn't obvious to me
> that all the other figures on the right, which I'd taken to be current
> usage, are actually (according to the chart) "next 12 months" projections.
>
> It'll be interesting to get Harry's take on the figures when he's done.
> Meanwhile, I'd still like to find out how 16% of respondents claimed to be
> using SystemC as a "verification language"; why I've never met any of these
> people; why 8% of verification engineers are still using Vera; why I don't
> know anyone who's still using Vera and why I haven't seen any Vera job
> postings for years; what actually qualifies as "SystemVerilog" usage; where
> the "next 12 months" projections come from; and so on.
>
>
> -Evan
>
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