Re: [vhdl-200x] Requirements to do verification

From: Jim Lewis <>
Date: Mon Apr 25 2011 - 23:41:04 PDT

All and Stephen,
First thing I would like to say is that I like Stephen and
I value his comments and input. It is good to have lots of
opinions - even differences of opinions. So whether you agree
or disagree with others, so please don't be shy about posting
your opinions. Expressing an opinion helps the group understand
the relative importance of a particular issue.

On the other hand, it is my belief that when posting
his companies marketing survey that Stephen violated
an IEEE rule and it is my responsibility as chair
to object to such behavior and stop it from continuing.
So please don't post any further quotes about marketing
surveys until we get a resolution on this issue.

For separate reasons, I agree that VHDL perhaps does not
need UVM. SystemVerilog needs UVM to supports its use
of OOP to model testbench models and to model connectivity
between testbench models. SV needs UVM because not only
does a model need to be concerned with connectivity, it
needs to separately be concerned with elaboration and
initialization fo a model. As a result, I see the same things
that Evan sees - with an OOP verification flow one needs
a separate group of specialists to do the verification.
I don't think we need or even want to be in this position.

For VHDL, I am hoping for something simple -
Keep things concurrent. While some see structural as RTL - I
see structural as concurrent program calls. One item we have
already identified for both RTL and verification is simplified
interfaces between structural models. To communicate through
the interfaces we will need some synchronization methods.
These methods and perhaps additional are needed anyway as
to do verification since we will need to synchronize
models that are otherwise independent to create interesting
test case scenarios.

I have enumerated other things in previous posts. I think
some capabilities such as basic randomization and functional
coverage can initially be done in packages with further
language support being added later.

What I would really like is your opinion. I would
particularly like to hear from Evan and Jonathan Bromley as
to what we are missing in our item list - I realize that
you may think I am silly to think I can implement many of
these things in VHDL packages, but humor me and let me know
what is missing and perhaps you will be surprised in the
end. I could really care less why you might think it is
not possible - simply items you think need to be done if
we are missing any so far.

I really would like to avoid situations, where we miss
something important simply because we failed to consult
someone with a better view point - such as the one I
found myself when I was backing out of a parking spot
in high school and scrapped the car on the passenger
side of mine. To this my friend in the passenger seat
said, "Dummy didn't you see that, I did." So again,
please speak up.

Best Regards,

Jim Lewis
Director of Training   
SynthWorks Design Inc. 
Expert VHDL Training for Hardware Design and Verification
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Received on Mon Apr 25 23:41:30 2011

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