Re: [vhdl-200x] Requirements to do verification

On 25/04/11 3:29 AM, Bailey, Stephen wrote:
> The future of VHDL is determined by the market (the aggregate of
> decisions made by individuals and individual corporations/entities).

The market is also influenced by large vendors. I've taken a hard look
through Harry Foster's slide set interested in why the growing interest in
random and constrained random testing. This is discernible in Parts 6 and
7, telling a story between expertise and less (directed) testing which
appears to be influence by design size. Design Engineers not primarily
engaged in verification. Tools empowering verification as a black box
become attractive when you separate the design knowledge domain from
verification.

Today there is nothing in VHDL that provides the ability to test without a
high degree of design knowledge and effort in part due tp lack of
verification features. The question is whether or not if those missing
features were added whether there would be any incentive to adopt a newer
and improved VHDL in that role.

In the mean time you have something like intelligent test bench automation
deprecating the need for some of these features. (We used to do the same
thing by hand to save on tester vector set load costs. At some point it's
about time, resources and cost.)

VHDL has been handicapped (hobbled) sometime in the past. Likely in favor
of other upcoming solutions and due to feature implementation lag. Trying
to fit in with the pack means missing the (next) wave. Some of us remember
how big a thing Vera seemed at one time. You'd imagine the only way to
wrest an established method of dealing with large designs today (1 M+ gates)
would be to get to the next big thing first, and as Mr. Bailey says there is
no investment in that.

Personally I'm of the opinion we'll see a paradigm shift first that'll
hobble everybody.

> Harry Foster has been reporting on the Mentor's blog the results of
> our blind survey of the verification market. In that survey, it is
> very clear that all languages are on the decline except SystemVerilog
> which is being adopted at an unprecedented rate and SystemC (as well
> as C/C++) which are relatively stable in usage. I reported the
> preliminary (North America only) data to this email list previously.
> Here's the world-wide data (languages used in verification):
>
> VHDL: 27% in 2007, 21% in 2010, 16% projected this year
> Verilog: 68%, 53%, 47%
> Vera: 11%, 8%, 3%
> SystemC: 17%, 16%, 19%
> SystemVerilog: 24%, 60%, 74%
> e: 16%, 15%, 11%
> C/C++: 30%, 35% and 32%
> Other: 5%, 3%, 2%
>

Page 53 of DVCon-2011.pdf See pages 56 - 58 as well, a keynote presentation
from Mr. Bailey's company. Page 56 includes by region (North Am,
Europe/Israel (Aus/NZ?), Asia, India). It'll show up in Google search.

The 'world wide' numbers don't appear quite so dire, year to year missing.

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