RE: [vhdl-200x] Why OOP vs Generics

Parameters: Analogous to variables in an equation. An operation has
operands but it can be programmed to work on any operand (of a specified
type).

Generics: It is a way of saying that an object (or function) has an
attribute but the specific details of the attribute are not important
within the object or function (beyond its existence) but is important
within the context that the object of function is used. For example,
all table objects have legs, but the legs of any table can be any color
and any shape (square, rectangle, conical, cylindrical, etc.). Or, my
exception handling routine must print out the exception information into
a log but it doesn't care how the exception information is formatted in
the log (assuming an ASCII log file). So, the using context can
provided a print routine that pretty prints for human reading our
generates CSV-compliant (Excel) output.

Both generics and parameterization can be fully used in design &
verification.

OOP: Is a way of structuring and organizing your system as a set of
objects that have specific identity. The identity would be the
attributes and behaviors that define the object. Inheritance permits a
hierarchical, conceptual organization of objects that share common
attributes. For example, a polygon is a generic 2-d geometric object
that has 3 or more sides, perimeter (sum of length of all sides), area
(equation dependent on polygon), angle between adjacent sides, and other
attributes. A triangle is a polygon with specifically 3 sides and its
specific equation for calculating area. An equilateral triangle has
sides of equal length. Etc. You gain economies in specification/design
by sharing common attributes in the inheritance hierarchy. The triangle
is a derivative of the polygon object and inherits all polygon
attributes. It is also said that a triangle object is a specialization
of polygon. Because it is well structured and avoids contradictions in
specification, OOP is appropriate for use in design & verification. OOP
limitations in hardware design (synthesis) are due to the prevalent
usage of dynamic OOP. However, it would be straight-forward to impose
static usage restrictions for support in HW design and synthesis.

AOP: Provides a way of redefining characteristics/behavior of an object
outside of the OOP inheritance framework. Technically, a specialized
object in OOP would never contradict attributes defined in the parent
(ancestor) objects. Such a contradiction would indicate a bad object
definition (over-specification at a higher level or inclusion of an
object that is not part of the conceptual hierarchy, at least not in
that position in the hierarchy). AOP has no such real or conceptually
ideal notion of contradiction or consistency. As such, it is my opinion
that AOP is unsuitable for design and implementation. However, it does
have value in verification. A very simple example: If a TB sequence
generator is programmed to generate only legal sequences, AOP could be
used to insert erroneous sequences to stress how the DUT handles bad
sequences. Unfortunately, the capabilities of AOP are often abused.
Extensive use of AOP can create debug nightmares, especially when
misused, because there is no structure to its use. But, properly used,
it can be valuable. SV does not have AOP support. A lot of the
capabilities of AOP are implemented via factories in OVM and UVM.

Generic packages in VHDL 2008 are the most complex and difficult
language feature to implement in that language version.

OOP and AOP are extremely difficult to get right in language design and
very difficult to properly implement in tools.

-Steve Bailey

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Joanne Degroat
Sent: Friday, March 18, 2011 12:52 PM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Why OOP vs Generics

Good question.

In the modeling I have done over the years I have used constants a bit
but
have never actually used generics.

Testbenches have been where I most use constants.

More discussion?

Joanne

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of
Jim Lewis
Sent: Thursday, March 17, 2011 6:29 PM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Why OOP vs Generics

Hi,
Martin asked a question in this mornings meeting:
why generics vs OOP/AOP programming? What are some
examples where we need OOP/AOP over using generics?
Particularly for testbenches.

I would like to open/provoke the discussion from there.

Best,
Jim

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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