Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

I still have copies of the VHDL+ documentation as PDFs. If anyone is
interested, I can deposit copies somewhere.

Mark Zwolinski

On 11/03/2011 16:58, Peter Flake wrote:
> Just a couple of comments:
>
> Many years ago there was a proposal called VHDL+ to add interfaces to VHDL.
> This was the inspiration for interfaces in SystemVerilog.
>
> I think it is still unclear whether object-orientation or aspect-orientation
> is better for verification code.
>
> Regards,
>
> Peter Flake
>
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
> David G. Koontz
> Sent: 11 March 2011 01:46
> To: vhdl-200x@eda.org
> Subject: Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list
>
> Jim has stated "My view is that OO is the base layer for building
> verification language features." Today that would imply signal based
> verification operation. If we look at earlier OO efforts (SUAVE, ooVHDL)
> these left VHDL largely intact and most of what they implied could be done
> purely with preprocessors.
>
> I happen to subscribe to the view expressed by Tim Schneider on adding
> abstraction to hierarchical interfaces in System Verilog, it's a short hand
> for not requiring another level of hierarchy otherwise needed to provide
> useful abstraction. It appears closely related to that which would be
> useful in simplify verification efforts, though from Ben's and Tim's point
> of view (and Jim's reply to Ben) everyone see's their favorite language as
> the center of the universe. (Which makes one wonder about an abstraction
> layer here beyond a particular language).
>
> The audience is wider than just verification although attractive enough for
> comparing various implementations (behavioral/system, RTL, gate). It can
> allow a third party to understand the structure of a model too, instead of
> being presented with VHDL netlists.
>
> I tried to find Jim's hinted recommendation but couldn't, nor Peter's
> (apparently) ESC-WP-001-oo-revisited.pdf from 2007, requiring a login to the
> Accellera VHDL effort culminating in VHDL-2008.
>
> From arm's length an interested reader can't tell the boundaries of the
> field or location of the goal posts in the paddock. How about a little
> foundational structure describing some limits? At this point all we can
> determine is who is interested in what subjects and some idea of how they
> achieved their views.
>
> It seems using the Twiki group page would be a good thing, potentionally
> allowing traceability to the problem being solved, the language used to
> describe the problem and solution and any pointers to any useful references.
> I'd imagine somewhere along the line it would also get properly organized
> for working group use.
>
> --
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>
>
>

-- 
===================================================================
Professor Mark Zwolinski
Electronic Systems & Devices Group       Tel. (+44) (0)23 8059 3528
Electronics & Computer Science           Fax. (+44) (0)23 8059 2901
University of Southampton                Email.  mz@ecs.soton.ac.uk
Southampton SO17 1BJ, UK             http://www.ecs.soton.ac.uk/~mz
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