Hi Scott,
> Since the digital portion of VHDL is at the hardware view,
> would it make more sense to just call it a pipeline delay
I agree. ShiftReg, Pipe, FF, REG, DFF, would
have some meaning to a large population. Had I not followed
David's previous thread, ZT would have confused me.
> P.S. is the anonymous identifier that Jim showed in his
> PipeReg procedure is that a valid VHDL identifier or is
> it a proposed identifier?
It is proposed, but if we decide to write ff/pipereg/mux,
it would be nice to write fewer versions, and hence,
my suggestion.
Best,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Feb 24 14:01:32 2011
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