Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

I am not sure we have to be concerned about this capability if you consider
that there are already several companies that support synthesizable
assertions and PSL is now part of VHDL. So in this case it becomes a
question of the synthesis vendor to support synthesisable PSL/SVA rather
than us modifying the assert construct, right?

Hans
www.ht-lab.com

From: Jonathan Ross
Sent: Thursday, February 24, 2011 4:10 PM
To: vhdl-200x@eda.org
Subject: Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list
Using assert is the proper way to do this. However, VHDL should support an
additional logical predicate - implies.

ASSERT X implies Y;

Implies can be implemented as "not X or Y", but having the keyword is
clearer. Most Satisfiability Modulo Theory solvers, which are often used to
optimize code, understand the implies statement directly. Some more
examples:

ASSERT X > 3 implies Y = 0;
ASSERT X = 1 implies (Y /= Z and Y > 3);

It's also useful anywhere an AND or OR could be used. Note that X implies Y
and Y implies X is not the same as X = Y. Implies is a predicate where as
equality is a binary function from items in some domain onto bool values
predicates may operate over. That said, it doesn't seem overly onerous to
language implementers to conflate equality and equivalence for these
purposes.

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