Re: [vhdl-200x] VHDL enhancements wish list

>>> On 18 February 2011 at 13:29, in message
<AANLkTi=Nxyy50DpJsnn-g2e2XifH-NbQP9z6UnCdnW9b@mail.gmail.com>, Daniel
Kho
<daniel.kho@gmail.com> wrote:
> Hi Martin,
>
> If Rst is in the sensitivity list, does this not imply an async
reset? And
> if not, then a sync reset?
>
> Yes, you're right. I think the intent of having Rst in the
sensitivity list
> together with specifying "synchronous" or "asynchronous" within the
process
> is to distinguish between the two.
>

That's my point - you don't need to specify it, the sensitivity list
already does (and we're all already used to doing so). Specifying it
twice allows you to get it wrong once :)

(For example currently you can intend an async reset, but get a sync
one:

process (clk)
being
if async reset = '1' then — this is actually a "both edges" sync
reset!
—
elseif rising_edge.....
end if

With a "just use the sensitivity list" approach, you can;t make that
mistake...

> Yes, we may need to evaluate how much gains this enhancement would
bring to
> the community. As for myself, I do try to use many small processes as
much
> as I can (sometimes with only several lines of code per process). I
do start
> with a big process in the beginning, but will try to break the
single
> process down into smaller processes.

Out of interest (and maybe reply to this off-list ;) why do you feel
theneed to break things down to very small processes?

Cheers,
Martin

-- 
Martin Thompson CEng MIET
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