Re: [vhdl-200x] VHDL enhancements wish list

From: Martin.J Thompson <Martin.J.Thompson@trw.com>
Date: Fri Feb 18 2011 - 01:12:06 PST

>>> On 18 February 2011 at 02:02, in message
<AANLkTimLg1_LDP=fcHEk=_GB6EpROziHOB2AX6y0ms2e@mail.gmail.com>, Daniel Kho
<daniel.kho@gmail.com> wrote:
> I was thinking of having another attribute just for these conditions, such
> as 'rising and 'falling attributes, so we can just specify:
> if clk'rising then
> or similarly do the same with the falling edge.
>
> Adding this idea to your original proposal (those if-statements are also
> still omitted), we could have something like:
> label: process(Rst, Clk'rising) is
> <synchronous | asynchronous> reset(Rst)

If Rst is in the sensitivity list, does this not imply an async reset? And if not, then a sync reset?

> -- reset logic
> begin
> -- non-reset logic
> end process;
>

I'm not sure what this gains though - unless your processes are very short, the lines of code overhead is negligible. Yes, there's a bit less boilerplate code, but a decent editor reduces that to a handful of keystrokes anyway.

Just my tuppence :)

Cheers,
Martin

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Received on Fri Feb 18 01:14:19 2011

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