[vhdl-200x] RE: Out of Bounds Discussion - VHDL IP encryption - key management

Hi Victor,
Thank you .
A point of clarification from the standards perspective. VHDL and Verilog include a standard encryption specification that, in principle, support interchangeable IP from multiple vendors. The 1735 activity is working on reconciling differences, clearing incomplete or inconsistent definitions, and extending support for encryption by making recommendations that both VHDL and SystemVerilog/Verilog can support.

I agree, if you care about this issue I would recommend that you participate in 1735 as well as your favorite language standard to make sure that it meets your needs.

Regards
David

David W. Smith
Synopsys Scientist
 
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124

Voice: 503.547.6467
Main:  503.547.6000
Cell:    503.560.5389
FAX:   503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
 
Saber Accelerates Robust Design
Predictable. Repeatable. Reliable. Proven.

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of victor
Sent: Wednesday, January 12, 2011 11:52 AM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Out of Bounds Discussion - VHDL IP encryption - key management

I would like to remind everyone that this reflector is for the discussion of IEEE standards ONLY. It is not a forum for the discussion of vendor tools in any shape or form. I understand that IP encryption is important to the industry. John Shields gave a very good summary of the activity going on at IEEE to standardize industry practice. I suggest that people interested in this activity join the appropriate Working Group.

I do not recognize Scott as a DASC member so perhaps he is not familiar with the rules that we operate under here so I would ask the chair to keep these discussions in bounds of the WG activity. Discussion of specific vendor tools and capabilities will jeopardize our indemnity from restraint of trade regulations under IEEE auspices.

Your cooperation is greatly appreciated.

 Victor

On 1/12/11 2:24 PM, "Hoy, Scott - IS" <Scott.Hoy@itt.com> wrote:

>
>
> -----Original Message-----
> From: Hoy, Scott - IS
> Sent: Wednesday, January 12, 2011 1:07 PM
> To: 'Jim Lewis'
> Subject: RE: [vhdl-200x] VHDL IP encryption - key management
>
> I would like the IP encryption scheme to be identical across all EDA
> tool vendors that say their tools comply with the associated IP
> encryption standard. The tool vendors I have discussed this with are
> Mentor Graphics, Synopsys, and Altera. The Synopsys encryption only
> work with Synopsys tools and the Mentor Graphics encryption referenced
> an IEEE encryption standard but I do not believe it was what the VHDL
> group is proposing. Mentor Graphics would keep the source code
> encrypted but the output EDIF or VQM file from synthesis would not be
> encrypted due to Altera and Xilinx are not compliant to the IEEE
> encryption they were using. When I inquired about key management,
> they said they do not allow the IP creator to mess with the key but
> only the cipher. In my opinion, for the IP encryption to take off,
> there needs to be a standard way for the IP creator to define and
> control the key. I would think a public/private key approach would be
> ideal, (I am not an encryption expert) . I also would think that for
> this to work, this may incur fees only on the IP creator to register a
> unique IP creator ID that can be used in the process to generate IP
> keys tied to a unique IP creator. The IP creator may qualify
> additional information to the unique IP creator ID that would further
> watermark IP generated key pairs that are licensed to users. When a
> user would license IP from an IP creator, the IP creator will release
> to the user the encrypted IP along with their unique public key that
> was generated in a process that used the IP creator's registered
> created ID. The user should be able to create a directory on their
> internal network that would store their licensed IP keys and set a unique environment variable that will point to this directory that all EDA tools that comply with the encryption standard should be able use in processing the encrypted IP.
>
> As an IP creator I want complete control over the key creation
> process. If the IEEE can standardize an encryption standard that does
> this, this would be a HUGE improvement on working with licensed IP.
> Currently, working with licensed IP can be a major PITA. To a degree,
> I would think that the encryption key creation/usage would work sort
> of how the EDA vendors use the FlexLM licensing to govern the
> licensing and usage of their tools. I kind of envision the unique
> creator ID to be similar to how Ethernet controller manufacturers (and
> Ethernet FPGA IP) register unique MAC addresses for their hardware/IP to function on an Ethernet network.
>
> From what I have read so far on the VHDL IP encryption, it covers how
> the IP creator can control what portions of code can be encrypted
> along with the type of encryption cipher to use but it is not clear as
> to how the IP creator can control and manage the encryption key that
> will be available for the tools to used to process the IP. If there
> is any documentation out there regarding how an IP creator can create and manage the encryption key, I would like to know.
>
> Scott D. Hoy
> E-mail: scott.hoy@itt.com
> Phone: 301-497-9900 Ext. 7162
> Fax: 301-497-0207
>
> ITT-AES
> 141 National Business Pkwy. Suite 200
> Annapolis Junction, MD 20701
> Phone: 301-497-9900 Fax: 301-497-0207
>
>
>
>
> -----Original Message-----
> From: Jim Lewis [mailto:Jim@SynthWorks.com]
> Sent: Wednesday, January 12, 2011 11:26 AM
> To: Hoy, Scott - IS
> Subject: Re: [vhdl-200x] VHDL IP encryption - key management
>
> Hi Scott,
> Oops. This was only meant to go directly to you.
> Please reply to me rather than the reflector.
> Jim
>
> Hi Scott,
> Is this for a specific tool?
> I can probably help you find the right person (if they don't contact
> you first).
>
> Best,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> --
> This message has been scanned for viruses and dangerous content by
> MailScanner, and is believed to be clean.
>
>
>
> This e-mail and any files transmitted with it may be proprietary and
> are intended solely for the use of the individual or entity to whom
> they are addressed. If you have received this e-mail in error please notify the sender.
> Please note that any views or opinions presented in this e-mail are
> solely those of the author and do not necessarily represent those of ITT Corporation.
> The recipient should check this e-mail and any attachments for the
> presence of viruses. ITT accepts no liability for any damage caused by
> any virus transmitted by this e-mail.

--
This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.