Re: [vhdl-200x] VHDL Meeting: January 10 at 8 am Pacific

Hi Hans,
The current problem (correct me if I am wrong) is not the
simulator/synthesis tools but P&R since the netlist out of synthesis into
P&R is still unencrypted which defeats the point somewhat.

I think there are synthesis tools out there that already gives the
capability to encrypt synthesis results for the P&R (though probably you
have to pay a premium for it). I know Altera has something called Design
Partitions (which is an encrypted synthesis partition which you can use with
other partitions, or on your top-level design, and perform P&R after
connecting them together). I think Xilinx and probably some other synthesis
tools do have that capability as well.

The problem here is that the encryption method is vendor-specific and does
not follow P1735. It will be good if we can put pressure on synthesis tool
vendors to use P1735 instead.

Regards,
Daniel

On Tue, Jan 11, 2011 at 5:36 PM, hans@ht-lab <hans64@ht-lab.com> wrote:

> Hi Charles,
>
> ----- Original Message ----- From: "Charles Gardiner" <
> gardiner.charles@vdi.de>
> To: <vhdl-200x@eda.org>
> Cc: "Jim Lewis" <Jim@synthworks.com>
> Sent: Monday, January 10, 2011 7:43 PM
> Subject: Re: [vhdl-200x] VHDL Meeting: January 10 at 8 am Pacific
>
>
>
> Hi Jim,
>>
>> luckily your meeting minutes haven't arrived yet so maybe I have a chnace
>> to put
>> in one more point I forgot at todays telco.
>>
>> Could you also put "Native language support for IP encryption (P1735?)" on
>> the
>> list? Encryption has been addressed with the most recent VHDL spec but I
>> would
>> like to make sure that VHDL is in sync with what P1735 ae doing.
>>
>> I already find this a very useful feature for giving customers
>> try-before-buy
>> solutions. At least Aldec provide a perl script for encrypting and the
>> compiler/simulator can read the encrypted files.
>> However, I think this is
>> currently restricted to a synplicity 'industry standard' encryption which
>> might be
>> a bit behind or different to what the P1735 are doing.
>>
>
> Just for completeness, Mentor's Precision also supports the P1735 standard
> as does Modelsim. You are right that there is no full support (Precision
> supports an early draft version) but I don't believe we have to be concerned
> about P1735 since there is already a lot of pressure to get full support for
> it.
>
> The current problem (correct me if I am wrong) is not the
> simulator/synthesis tools but P&R since the netlist out of synthesis into
> P&R is still unencrypted which defeats the point somewhat.
>
> Regards,
> Hans.
> www.ht-lab.com
>
>
>
>
> I would see this firstly as
>> a point for review and action only required if necessary.
>>
>> --
>> Best regards,
>> Mit freundlichen Gruessen,
>>
>> Charles
>>
>> -------------------------------------------------------------
>> Ing. Buero Gardiner
>> Heuglinstr. 29a
>> D-81249 Muenchen
>>
>> Email: mailto:gardiner.charles@vdi.de
>> Phone: +49 89/1400 6955, Mobile +49 171/867 2732
>> Fax : +49 89/8638 9764
>>
>> asic, eda, embedded hw/sw, fpga
>> soc, system verification
>>
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