Ben - I have no intention of getting involved in this debate, but I do
have to set the record straight on one point - all this stuff was done
cleanly and concisely, in 'e', nearly 20 years ago, long before
SystemVerilog re-invented the wheel. If anyone wants comparison data
points, then SV is very much the wrong place to look. SV exists for a
complex set of reasons which have nothing to do with technical merit.
I might also point out Peter Flake's comment:
> One could consider that
> e and PSL fulfil the roles of testbench and assertions
-Evan
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