Re: [vhdl-200x] Request for Input

I haven't contributed to any of this for many years, but I have a high
regard for VHDL and its protagonists, and it would be irresponsible
of me to leave this unsaid.

I don't at all like the way this discussion is going and I think you
need to be just a touch pragmatic here.

No-one in EDA land is even going to bother to yawn if you
suggest they use OO Ada or anything like it.

No-one in EDA land is, at this late stage, going to put in the
investment to build production quality OO extensions to VHDL.

VHDL has unique existing strengths that you should be shouting about
very loudly. As someone who's currently struggling with implementation
of fixed-point in various parts of a SystemVerilog verification project, I'm
pretty jealous of how easy that was in VHDL (easy in principle, though
of course I also know how much work went into making a good job
of it - no slight intended!). But VHDL is too severely hobbled by its
historical baggage to make the running in the heavy-duty verification
space. Two minutes' thought about its creaky file I/O and string
handling will tell you that. Strings and files matter to verification folk.

For what it's worth, my $0.02 is that you should do NOTHING about
extending VHDL, but instead you should bust a gut to throw wide
open the interfaces to it. Make it *really* easy and *really*
efficient to use it with great slabs of C++ in a testbench. Make
it *really* easy, effective and *standardized* to use VHDL with any
of the zoo of script languages that people like to use to make their
verification more interactive and flexible (Tcl, Python, Ruby). Allow
people to use an existing script language to do string and file
manipulation, right there from within the VHDL source code.
Think very hard about robust, standardized interfaces to other
ways of describing stuff (think XML/IP-XACT, for instance).

Ask your users why it's such a pain to use VHPI (or Verilog VPI,
come to that) and what they would like to see to make it easier
to integrate other software tools. (Hint: It would be MUCH easier
to browse a design hierarchy using a scripting language than
using C/C++.)

And finally, talk to the UPF people about low-power modelling,
and maybe have a little think about a successor to std_logic_1164
that knows something about power domains.

In other words, instead of playing a suicidally expensive
game of catch-up-with-SV that you can't possibly win, think
about how to leapfrog it.

OK, I've said it - no responses required or expected.
Thanks for listening.

Jonathan Bromley

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