FW: [vhdl-200x] Call for Vote on Group Organization and PAR

From: Bailey, Stephen <stephen_bailey@mentor.com>
Date: Sun Dec 19 2010 - 12:35:16 PST

I have submitted my negative vote on the PAR to Jim. I am now
forwarding the comments that document why I am voting Negative.

-Steve Bailey

The SG has spent all of its time discussing the organization of the WG
as individual or entity/Corporate. I don't see anything in the minutes
identifying the requirements for this revision. The recent flurry of
emails has me concerned that the WG will duplicate significant work that
has gone into SV by putting similar functionality into VHDL. I cannot
support the waste of tens to hundreds of man-years to achieve that
output with the only outcome being that people can do what they can do
today only in 2 different languages instead of 1 (actually 4 different
languages instead of 3 when you include e and Vera).

VHDL usage was on the decline prior to SV. SV has accelerated that
decline. I don't see a way to change the current course of the
EDA/language trends. They are too strong and the cost to change them
are prohibitive.

Data which the SG may find useful. The data is from a recent blind
survey commissioned by Mentor and conducted by Wilson Research Group.
This data is from North America. The rest of the world portion of the
survey was recently completed and the combined results not yet
available.

VHDL design usage declined from 37% in 2007 to 27% in 2010 with
respondents projected a further decline to 23% in the next 12 months.
That's a loss of nearly 40% of the design user base for VHDL.

Verilog usage has declined from 81% to 78% and projected to go to 71%.
SystemC, C/C++ and other design languages have also declined from 2007
to 2010.

SV has increased from 10% to 34% today and projected to reach 47% in the
next year. That's a nearly 5x increase in usage.

In verification, VHDL usage is down to 21%, from 27%, and projected to
fall further. In fact, there are only two languages that have increased
usage in verification: SystemVerilog usage in verification more than
doubled to 50% and is projected to increase significantly in the next
year. C/C++ has seen a respectable increase from 2007 but is projected
to decline slightly in the next year. Even SystemC usage in
verification is down slightly from 2007 -- call it steady at about 17%.

The survey included FPGA and ASIC designs and respondents from all
industries/markets. Although data from the rest of the world might
soften a bit what is being reported in NA, based on my personal
experience, I don't expect it to be meaningful in any area except maybe
SystemC, which has historically higher use in Europe and Japan than in
the U.S.

In the next year, 80% (4 of every 5) of designers and verification
engineers will use a language that is not VHDL. Most of them will be
using SV or Verilog.

The SG needs to ask itself these questions: Can you stop a tsunami?
What can you offer that would overcome a projected 3x+ advantage that SV
will have over VHDL in verification usage within the next year; and
surely greater than that 2 or 3 years from now. If the plan is to
survive the tsunami, what will you do to survive it when EDA vendors
clearly know where the market is going? Until these questions are
addressed in a manner that reflects reality, my vote will remain No on
another VHDL language revision.

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Received on Sun Dec 19 12:35:38 2010

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