[vhdl-200x] Re: [Accellera:vhdl] VHDL Study Group Meeting Notice

I have to agree with Collin. It seems that the membership in DASC is on
the decline,
and the number of people who are eligible to vote are also on the decline
as well.
Instead of fostering involvement of the users of the actual language and
associated
tools (simulators/compilers/synthesis & route tools), it seems that what is
being
proposed will force these people away from getting involved -- the vendors
and
Academia will not benefit from the real-life users of VHDL and what they
see
are current weaknesses and what they envision could be implemented in
future updates to the VHDL language.

I know that I've had trouble over the last several years in getting my
company
to fund my attending either HDLCON or DAC (missing out on the face-2-face
meetings). I cannot justify to them how my participating will benefit the
company.
All, if any, contributions that I can currently make is on balloting
efforts and
maybe some comments that come out of Accellera's developed versions
of the next update to the language (DASC used to handle it with the VIUF
conference and have users post). I can honestly say that the amount
of email reflector traffic that I've seen over the last 10 years has
dropped
a good amount, especially for the last 5.

I believe that there needs to be some changes made to get the users
more actively involved with suggesting changes, participating, etc. --
it appears that we're going in the opposite direction.

Regards,
Bob

Robert J. Myers
HW/FPGA Designer -- HSS/DAS
Raytheon
2501 W. University M/S 8016
McKinney, Tx. 75070
(972)952-3587

                                                                                                                           
  From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
                                                                                                                           
  To: Accellera VHDL TC <vhdl@lists.accellera.org>
                                                                                                                           
  Cc: "vhdl-200x@eda.org" <vhdl-200x@EDA.org>, DASC <stds-dasc@DASC.org>, Accellera VHDL Extensions
              <vhdl-ext@lists.accellera.org>, vhdl-lrm <vhdl-lrm@lists.accellera.org>, isac@EDA.org
                                                                                                                           
  Date: 11/09/2010 03:52 AM
                                                                                                                           
  Subject: Re: [Accellera:vhdl] VHDL Study Group Meeting Notice
                                                                                                                           
  Sent by: <vhdl@lists.accellera.org>
                                                                                                                           

Jim Lewis <Jim@SynthWorks.com> sent on November 8th, 2010:

|------------------------------------------------------------|
|"[..] |
| |
|Meeting is scheduled for Wednesday Dec 1 at 8 am Pacific. |
|Dial in details will be announced later. |
| |
|[..] |
| |
|One item that will come up is whether to organize the VHDL |
|working group as an individual (as it has been) or corporate|
|based working group. Anyone with a vested interest in VHDL |
|can participate (attend meetings, be on the working group |
|email reflector, and attain voting rights) in an individual |
|based working group. In a corporate based working group, |
|to be an observer (attend meetings or be on the reflector) |
|will cost a company between $1250 and $5500 (depending on |
|corporate revenue). To be a voting member, one must be |
|an advanced corporate member at a cost of $3500 to $10000. |
|Unfortunately none of this money goes to the working group, |
|instead it goes to fund IEEE Standards Association (which |
|is a separate organization from IEEE). Any funding needed |
|by the working group will be a separate assessment. |
| |
|[..]" |
|------------------------------------------------------------|

Hi,

I shall probably not be in a position to dial in, but I wish you
and VHDL success.

I suggest that forcing participants to pay to participate would
benefit bankers' bank accounts and raise prices for VHDL tools without
corresponding improvements to those tools. VHDL should evolve on a
basis of technical merit instead of on a basis of bribes. VHDL's
progress should not be kept secret: we want engineers to adopt VHDL.

With kind regards,
Colin Paul Gloster

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