[vhdl-200x] implicit conversions

Dear list,

VHDL v2008 added a lot of implicit conversions, especially for
conditions. The condition can be of either BOOLEAN, BIT or STD_ULOGIC
type. I would like to go one step further and to allow implicit
conversions for integer types. When an expression type is determined by
the context to be an INTEGER, the language should accept expressions of
IEEE.NUMERIC_STD.SIGNED and IEEE.NUMERIC_BIT.SIGNED types.

For instance, lets consider the following statements:

signal some_index: unsigned(7 downto 0);
signal some_vector: std_logic_vector(255 downto 0);
signal some_output: std_logic;

Presently, the designer has to call either IEEE.NUMERIC_STD.TO_INTEGER
or IEEE.NUMERIC_BIT.TO_INTEGER. However, these function calls are
transparent at hardware level:

some_output <= some_vector(to_integer(some_index));

I would like to make this statement valid:

Some_output <= some_vector(some_index);

Of course, the behaviour of the implicit conversions shall be the same
as the behaviour of TO_INTEGER functions. These implicit conversions
shall be allowed every time the context expects some expression of type
integer.

Best regards,

-- 
Florent Ouchet
PhD Student
CIS/VDS Team - TIMA Laboratory
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